| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s |
| # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s |
| |
| --- |
| name: reg_sequence_ss_vreg |
| legalized: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0, $sgpr1 |
| |
| ; CHECK-LABEL: name: reg_sequence_ss_vreg |
| ; CHECK: liveins: $sgpr0, $sgpr1 |
| ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 |
| ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr(s64) = REG_SEQUENCE [[COPY]](s32), %subreg.sub0, [[COPY1]](s32), %subreg.sub1 |
| %0:_(s32) = COPY $sgpr0 |
| %1:_(s32) = COPY $sgpr1 |
| %2:_(s64) = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1 |
| ... |
| |
| --- |
| name: reg_sequence_ss_physreg |
| legalized: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0, $sgpr1 |
| |
| ; CHECK-LABEL: name: reg_sequence_ss_physreg |
| ; CHECK: liveins: $sgpr0, $sgpr1 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $sgpr1, %subreg.sub1 |
| %0:_(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $sgpr1, %subreg.sub1 |
| ... |
| |
| --- |
| name: reg_sequence_sv_vreg |
| legalized: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0, $vgpr0 |
| |
| ; CHECK-LABEL: name: reg_sequence_sv_vreg |
| ; CHECK: liveins: $sgpr0, $vgpr0 |
| ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 |
| ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE [[COPY]](s32), %subreg.sub0, [[COPY1]](s32), %subreg.sub1 |
| %0:_(s32) = COPY $sgpr0 |
| %1:_(s32) = COPY $vgpr0 |
| %2:_(s64) = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1 |
| ... |
| |
| --- |
| name: reg_sequence_sv_physreg |
| legalized: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0, $vgpr0 |
| |
| ; CHECK-LABEL: name: reg_sequence_sv_physreg |
| ; CHECK: liveins: $sgpr0, $vgpr0 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $vgpr0, %subreg.sub1 |
| %0:_(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $vgpr0, %subreg.sub1 |
| ... |
| |
| --- |
| name: reg_sequence_vs_vreg |
| legalized: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $vgpr0, $sgpr0 |
| |
| ; CHECK-LABEL: name: reg_sequence_vs_vreg |
| ; CHECK: liveins: $vgpr0, $sgpr0 |
| ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 |
| ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE [[COPY]](s32), %subreg.sub0, [[COPY1]](s32), %subreg.sub1 |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $sgpr0 |
| %2:_(s64) = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1 |
| ... |
| |
| --- |
| name: reg_sequence_vs_physreg |
| legalized: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $vgpr0, $sgpr0 |
| |
| ; CHECK-LABEL: name: reg_sequence_vs_physreg |
| ; CHECK: liveins: $vgpr0, $sgpr0 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE $vgpr0, %subreg.sub0, $sgpr0, %subreg.sub1 |
| %0:_(s64) = REG_SEQUENCE $vgpr0, %subreg.sub0, $sgpr0, %subreg.sub1 |
| ... |
| |
| --- |
| name: reg_sequence_vv_vreg |
| legalized: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1 |
| |
| ; CHECK-LABEL: name: reg_sequence_vv_vreg |
| ; CHECK: liveins: $vgpr0, $vgpr1 |
| ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 |
| ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE [[COPY]](s32), %subreg.sub0, [[COPY1]](s32), %subreg.sub1 |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(s64) = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1 |
| ... |
| |
| --- |
| name: reg_sequence_vv_physreg |
| legalized: true |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1 |
| |
| ; CHECK-LABEL: name: reg_sequence_vv_physreg |
| ; CHECK: liveins: $vgpr0, $vgpr1 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE $vgpr0, %subreg.sub0, $vgpr1, %subreg.sub1 |
| %0:_(s64) = REG_SEQUENCE $vgpr0, %subreg.sub0, $vgpr1, %subreg.sub1 |
| ... |
| |