commit c7464a4ca2c15cbe3d814f23324e11541847d2c0
author Craig Topper <craig.topper@intel.com> Mon Oct 14 23:48:24 2019 +0000
committer Craig Topper <craig.topper@intel.com> Mon Oct 14 23:48:24 2019 +0000
tree 902793641e25fdafd5c5f10fbfd8a79331b73cb0
parent d74926b4d5f1a2d0219ca47da63006205e731649

[X86] Teach X86MCodeEmitter to properly encode zmm16-zmm31 as index register to vgatherpf/vscatterpf.

We need to encode bit 4 into the EVEX.V' bit. We do this right
for regular gather/scatter which use either MRMSrcMem or MRMDestMem
formats.  The prefetches use MRM*m formats.

Fixes an issue recently added to PR36202.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@374849 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp

diff --git a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
index 31d26d0..ac36bf3 100644
--- a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
+++ b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
@@ -862,6 +862,9 @@
     VEX_B = ~(BaseRegEnc >> 3) & 1;
     unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg);
     VEX_X = ~(IndexRegEnc >> 3) & 1;
+    if (!HasVEX_4V) // Only needed with VSIB which don't use VVVV.
+      EVEX_V2 = ~(IndexRegEnc >> 4) & 1;
+
     break;
   }
   case X86II::MRMSrcReg: {

test/MC/X86/x86-64-avx512pf.s

diff --git a/test/MC/X86/x86-64-avx512pf.s b/test/MC/X86/x86-64-avx512pf.s
index 6cbf255..bae7fb0 100644
--- a/test/MC/X86/x86-64-avx512pf.s
+++ b/test/MC/X86/x86-64-avx512pf.s
@@ -1,23 +1,23 @@
 // RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
 
 // CHECK: vgatherpf0dps (%r8,%zmm20) {%k1}
-// CHECK: encoding: [0x62,0xd2,0x7d,0x49,0xc6,0x0c,0x20]
+// CHECK: encoding: [0x62,0xd2,0x7d,0x41,0xc6,0x0c,0x20]
 vgatherpf0dps (%r8,%zmm20){%k1}
 
 // CHECK: vgatherpf1dps (%r9,%zmm19) {%k2}
-// CHECK: encoding: [0x62,0xd2,0x7d,0x4a,0xc6,0x14,0x19]
+// CHECK: encoding: [0x62,0xd2,0x7d,0x42,0xc6,0x14,0x19]
 vgatherpf1dps (%r9,%zmm19){%k2}
 
 // CHECK: vgatherpf0dpd (%r10,%ymm18) {%k3}
-// CHECK: encoding: [0x62,0xd2,0xfd,0x4b,0xc6,0x0c,0x12]
+// CHECK: encoding: [0x62,0xd2,0xfd,0x43,0xc6,0x0c,0x12]
 vgatherpf0dpd (%r10,%ymm18){%k3}
 
 // CHECK: vgatherpf1dpd (%r11,%ymm17) {%k4}
-// CHECK: encoding: [0x62,0xd2,0xfd,0x4c,0xc6,0x14,0x0b]
+// CHECK: encoding: [0x62,0xd2,0xfd,0x44,0xc6,0x14,0x0b]
 vgatherpf1dpd (%r11,%ymm17){%k4}
 
 // CHECK: vgatherpf0qps (%r12,%zmm16) {%k5}
-// CHECK: encoding: [0x62,0xd2,0x7d,0x4d,0xc7,0x0c,0x04]
+// CHECK: encoding: [0x62,0xd2,0x7d,0x45,0xc7,0x0c,0x04]
 vgatherpf0qps (%r12,%zmm16){%k5}
 
 // CHECK: vgatherpf1qps (%r13,%zmm15) {%k6}
@@ -33,23 +33,23 @@
 vgatherpf1qpd (%r15,%zmm13){%k1}
 
 // CHECK: vscatterpf0dps (%r8,%zmm20) {%k1}
-// CHECK: encoding: [0x62,0xd2,0x7d,0x49,0xc6,0x2c,0x20]
+// CHECK: encoding: [0x62,0xd2,0x7d,0x41,0xc6,0x2c,0x20]
 vscatterpf0dps (%r8,%zmm20){%k1}
 
 // CHECK: vscatterpf1dps (%r9,%zmm19) {%k2}
-// CHECK: encoding: [0x62,0xd2,0x7d,0x4a,0xc6,0x34,0x19]
+// CHECK: encoding: [0x62,0xd2,0x7d,0x42,0xc6,0x34,0x19]
 vscatterpf1dps (%r9,%zmm19){%k2}
 
 // CHECK: vscatterpf0dpd (%r10,%ymm18) {%k3}
-// CHECK: encoding: [0x62,0xd2,0xfd,0x4b,0xc6,0x2c,0x12]
+// CHECK: encoding: [0x62,0xd2,0xfd,0x43,0xc6,0x2c,0x12]
 vscatterpf0dpd (%r10,%ymm18){%k3}
 
 // CHECK: vscatterpf1dpd (%r11,%ymm17) {%k4}
-// CHECK: encoding: [0x62,0xd2,0xfd,0x4c,0xc6,0x34,0x0b]
+// CHECK: encoding: [0x62,0xd2,0xfd,0x44,0xc6,0x34,0x0b]
 vscatterpf1dpd (%r11,%ymm17){%k4}
 
 // CHECK: vscatterpf0qps (%r12,%zmm16) {%k5}
-// CHECK: encoding: [0x62,0xd2,0x7d,0x4d,0xc7,0x2c,0x04]
+// CHECK: encoding: [0x62,0xd2,0x7d,0x45,0xc7,0x2c,0x04]
 vscatterpf0qps (%r12,%zmm16){%k5}
 
 // CHECK: vscatterpf1qps (%r13,%zmm15) {%k6}