| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s -enable-var-scope -check-prefixes=FUNC,GCN,SI |
| ; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s -enable-var-scope -check-prefixes=FUNC,GCN,VI |
| ; RUN: llc < %s -march=r600 -mcpu=cypress -verify-machineinstrs | FileCheck %s -enable-var-scope -check-prefixes=FUNC,EG |
| |
| declare i7 @llvm.ctlz.i7(i7, i1) nounwind readnone |
| declare i8 @llvm.ctlz.i8(i8, i1) nounwind readnone |
| declare i16 @llvm.ctlz.i16(i16, i1) nounwind readnone |
| |
| declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone |
| declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone |
| declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone |
| |
| declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone |
| declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) nounwind readnone |
| declare <4 x i64> @llvm.ctlz.v4i64(<4 x i64>, i1) nounwind readnone |
| |
| declare i32 @llvm.r600.read.tidig.x() nounwind readnone |
| |
| define amdgpu_kernel void @s_ctlz_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind { |
| ; SI-LABEL: s_ctlz_i32: |
| ; SI: ; %bb.0: |
| ; SI-NEXT: s_load_dword s2, s[0:1], 0xb |
| ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 |
| ; SI-NEXT: s_mov_b32 s7, 0xf000 |
| ; SI-NEXT: s_waitcnt lgkmcnt(0) |
| ; SI-NEXT: s_flbit_i32_b32 s0, s2 |
| ; SI-NEXT: s_mov_b32 s6, -1 |
| ; SI-NEXT: v_mov_b32_e32 v0, s0 |
| ; SI-NEXT: v_cmp_ne_u32_e64 vcc, s2, 0 |
| ; SI-NEXT: v_cndmask_b32_e32 v0, 32, v0, vcc |
| ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 |
| ; SI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: s_ctlz_i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 |
| ; VI-NEXT: s_load_dword s0, s[0:1], 0x2c |
| ; VI-NEXT: s_mov_b32 s7, 0xf000 |
| ; VI-NEXT: s_mov_b32 s6, -1 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_flbit_i32_b32 s1, s0 |
| ; VI-NEXT: v_mov_b32_e32 v0, s1 |
| ; VI-NEXT: v_cmp_ne_u32_e64 vcc, s0, 0 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, 32, v0, vcc |
| ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; EG-LABEL: s_ctlz_i32: |
| ; EG: ; %bb.0: |
| ; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 |
| ; EG-NEXT: CF_END |
| ; EG-NEXT: PAD |
| ; EG-NEXT: ALU clause starting at 4: |
| ; EG-NEXT: FFBH_UINT * T0.W, KC0[2].Z, |
| ; EG-NEXT: CNDE_INT T0.X, KC0[2].Z, literal.x, PV.W, |
| ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, |
| ; EG-NEXT: 32(4.484155e-44), 2(2.802597e-45) |
| %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 false) nounwind readnone |
| store i32 %ctlz, i32 addrspace(1)* %out, align 4 |
| ret void |
| } |
| |
| define amdgpu_kernel void @v_ctlz_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { |
| ; SI-LABEL: v_ctlz_i32: |
| ; SI: ; %bb.0: |
| ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 |
| ; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb |
| ; SI-NEXT: s_mov_b32 s7, 0xf000 |
| ; SI-NEXT: s_mov_b32 s10, 0 |
| ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 |
| ; SI-NEXT: v_mov_b32_e32 v1, 0 |
| ; SI-NEXT: s_mov_b32 s11, s7 |
| ; SI-NEXT: s_waitcnt lgkmcnt(0) |
| ; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64 |
| ; SI-NEXT: s_mov_b32 s6, -1 |
| ; SI-NEXT: s_waitcnt vmcnt(0) |
| ; SI-NEXT: v_ffbh_u32_e32 v1, v0 |
| ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 |
| ; SI-NEXT: v_cndmask_b32_e32 v0, 32, v1, vcc |
| ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 |
| ; SI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: v_ctlz_i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c |
| ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 |
| ; VI-NEXT: s_mov_b32 s7, 0xf000 |
| ; VI-NEXT: s_mov_b32 s6, -1 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v1, s1 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 |
| ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; VI-NEXT: flat_load_dword v0, v[0:1] |
| ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_ffbh_u32_e32 v1, v0 |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, 32, v1, vcc |
| ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; EG-LABEL: v_ctlz_i32: |
| ; EG: ; %bb.0: |
| ; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: TEX 0 @6 |
| ; EG-NEXT: ALU 3, @11, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 |
| ; EG-NEXT: CF_END |
| ; EG-NEXT: PAD |
| ; EG-NEXT: Fetch clause starting at 6: |
| ; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 |
| ; EG-NEXT: ALU clause starting at 8: |
| ; EG-NEXT: LSHL * T0.W, T0.X, literal.x, |
| ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) |
| ; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, |
| ; EG-NEXT: ALU clause starting at 11: |
| ; EG-NEXT: FFBH_UINT * T0.W, T0.X, |
| ; EG-NEXT: CNDE_INT T0.X, T0.X, literal.x, PV.W, |
| ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, |
| ; EG-NEXT: 32(4.484155e-44), 2(2.802597e-45) |
| %tid = call i32 @llvm.r600.read.tidig.x() |
| %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid |
| %val = load i32, i32 addrspace(1)* %in.gep, align 4 |
| %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 false) nounwind readnone |
| store i32 %ctlz, i32 addrspace(1)* %out, align 4 |
| ret void |
| } |
| |
| define amdgpu_kernel void @v_ctlz_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrspace(1)* noalias %valptr) nounwind { |
| ; SI-LABEL: v_ctlz_v2i32: |
| ; SI: ; %bb.0: |
| ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 |
| ; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb |
| ; SI-NEXT: s_mov_b32 s7, 0xf000 |
| ; SI-NEXT: s_mov_b32 s10, 0 |
| ; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 |
| ; SI-NEXT: v_mov_b32_e32 v1, 0 |
| ; SI-NEXT: s_mov_b32 s11, s7 |
| ; SI-NEXT: s_waitcnt lgkmcnt(0) |
| ; SI-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[8:11], 0 addr64 |
| ; SI-NEXT: s_mov_b32 s6, -1 |
| ; SI-NEXT: s_waitcnt vmcnt(0) |
| ; SI-NEXT: v_ffbh_u32_e32 v2, v1 |
| ; SI-NEXT: v_ffbh_u32_e32 v3, v0 |
| ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; SI-NEXT: v_cndmask_b32_e32 v1, 32, v2, vcc |
| ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 |
| ; SI-NEXT: v_cndmask_b32_e32 v0, 32, v3, vcc |
| ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 |
| ; SI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: v_ctlz_v2i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c |
| ; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 |
| ; VI-NEXT: s_mov_b32 s7, 0xf000 |
| ; VI-NEXT: s_mov_b32 s6, -1 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v1, s1 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 |
| ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] |
| ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_ffbh_u32_e32 v2, v1 |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: v_cndmask_b32_e32 v1, 32, v2, vcc |
| ; VI-NEXT: v_ffbh_u32_e32 v3, v0 |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, 32, v3, vcc |
| ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; EG-LABEL: v_ctlz_v2i32: |
| ; EG: ; %bb.0: |
| ; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: TEX 0 @6 |
| ; EG-NEXT: ALU 6, @11, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 |
| ; EG-NEXT: CF_END |
| ; EG-NEXT: PAD |
| ; EG-NEXT: Fetch clause starting at 6: |
| ; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1 |
| ; EG-NEXT: ALU clause starting at 8: |
| ; EG-NEXT: LSHL * T0.W, T0.X, literal.x, |
| ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) |
| ; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, |
| ; EG-NEXT: ALU clause starting at 11: |
| ; EG-NEXT: FFBH_UINT * T0.W, T0.Y, |
| ; EG-NEXT: CNDE_INT T0.Y, T0.Y, literal.x, PV.W, |
| ; EG-NEXT: FFBH_UINT * T0.W, T0.X, |
| ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) |
| ; EG-NEXT: CNDE_INT T0.X, T0.X, literal.x, PV.W, |
| ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, |
| ; EG-NEXT: 32(4.484155e-44), 2(2.802597e-45) |
| %tid = call i32 @llvm.r600.read.tidig.x() |
| %in.gep = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %valptr, i32 %tid |
| %val = load <2 x i32>, <2 x i32> addrspace(1)* %in.gep, align 8 |
| %ctlz = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %val, i1 false) nounwind readnone |
| store <2 x i32> %ctlz, <2 x i32> addrspace(1)* %out, align 8 |
| ret void |
| } |
| |
| define amdgpu_kernel void @v_ctlz_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %valptr) nounwind { |
| ; SI-LABEL: v_ctlz_v4i32: |
| ; SI: ; %bb.0: |
| ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 |
| ; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb |
| ; SI-NEXT: s_mov_b32 s7, 0xf000 |
| ; SI-NEXT: s_mov_b32 s10, 0 |
| ; SI-NEXT: v_lshlrev_b32_e32 v0, 4, v0 |
| ; SI-NEXT: v_mov_b32_e32 v1, 0 |
| ; SI-NEXT: s_mov_b32 s11, s7 |
| ; SI-NEXT: s_waitcnt lgkmcnt(0) |
| ; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64 |
| ; SI-NEXT: s_mov_b32 s6, -1 |
| ; SI-NEXT: s_waitcnt vmcnt(0) |
| ; SI-NEXT: v_ffbh_u32_e32 v4, v3 |
| ; SI-NEXT: v_ffbh_u32_e32 v5, v2 |
| ; SI-NEXT: v_ffbh_u32_e32 v6, v1 |
| ; SI-NEXT: v_ffbh_u32_e32 v7, v0 |
| ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; SI-NEXT: v_cndmask_b32_e32 v3, 32, v4, vcc |
| ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; SI-NEXT: v_cndmask_b32_e32 v2, 32, v5, vcc |
| ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; SI-NEXT: v_cndmask_b32_e32 v1, 32, v6, vcc |
| ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 |
| ; SI-NEXT: v_cndmask_b32_e32 v0, 32, v7, vcc |
| ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 |
| ; SI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: v_ctlz_v4i32: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c |
| ; VI-NEXT: v_lshlrev_b32_e32 v0, 4, v0 |
| ; VI-NEXT: s_mov_b32 s7, 0xf000 |
| ; VI-NEXT: s_mov_b32 s6, -1 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v1, s1 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 |
| ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1] |
| ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_ffbh_u32_e32 v4, v3 |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; VI-NEXT: v_cndmask_b32_e32 v3, 32, v4, vcc |
| ; VI-NEXT: v_ffbh_u32_e32 v5, v2 |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; VI-NEXT: v_cndmask_b32_e32 v2, 32, v5, vcc |
| ; VI-NEXT: v_ffbh_u32_e32 v6, v1 |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: v_cndmask_b32_e32 v1, 32, v6, vcc |
| ; VI-NEXT: v_ffbh_u32_e32 v7, v0 |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, 32, v7, vcc |
| ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; EG-LABEL: v_ctlz_v4i32: |
| ; EG: ; %bb.0: |
| ; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: TEX 0 @6 |
| ; EG-NEXT: ALU 12, @11, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1 |
| ; EG-NEXT: CF_END |
| ; EG-NEXT: PAD |
| ; EG-NEXT: Fetch clause starting at 6: |
| ; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1 |
| ; EG-NEXT: ALU clause starting at 8: |
| ; EG-NEXT: LSHL * T0.W, T0.X, literal.x, |
| ; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00) |
| ; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, |
| ; EG-NEXT: ALU clause starting at 11: |
| ; EG-NEXT: FFBH_UINT * T1.W, T0.W, |
| ; EG-NEXT: FFBH_UINT T2.W, T0.Z, |
| ; EG-NEXT: CNDE_INT * T0.W, T0.W, literal.x, PV.W, BS:VEC_021/SCL_122 |
| ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) |
| ; EG-NEXT: CNDE_INT T0.Z, T0.Z, literal.x, PV.W, |
| ; EG-NEXT: FFBH_UINT * T1.W, T0.Y, |
| ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) |
| ; EG-NEXT: CNDE_INT T0.Y, T0.Y, literal.x, PV.W, |
| ; EG-NEXT: FFBH_UINT * T1.W, T0.X, |
| ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) |
| ; EG-NEXT: CNDE_INT T0.X, T0.X, literal.x, PV.W, |
| ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, |
| ; EG-NEXT: 32(4.484155e-44), 2(2.802597e-45) |
| %tid = call i32 @llvm.r600.read.tidig.x() |
| %in.gep = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %valptr, i32 %tid |
| %val = load <4 x i32>, <4 x i32> addrspace(1)* %in.gep, align 16 |
| %ctlz = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %val, i1 false) nounwind readnone |
| store <4 x i32> %ctlz, <4 x i32> addrspace(1)* %out, align 16 |
| ret void |
| } |
| |
| define amdgpu_kernel void @v_ctlz_i8(i8 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %valptr) nounwind { |
| ; SI-LABEL: v_ctlz_i8: |
| ; SI: ; %bb.0: |
| ; SI-NEXT: s_mov_b32 s3, 0xf000 |
| ; SI-NEXT: s_mov_b32 s2, -1 |
| ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb |
| ; SI-NEXT: s_mov_b32 s6, s2 |
| ; SI-NEXT: s_mov_b32 s7, s3 |
| ; SI-NEXT: s_waitcnt lgkmcnt(0) |
| ; SI-NEXT: buffer_load_ubyte v0, off, s[4:7], 0 |
| ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 |
| ; SI-NEXT: s_waitcnt vmcnt(0) |
| ; SI-NEXT: v_ffbh_u32_e32 v1, v0 |
| ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 |
| ; SI-NEXT: v_cndmask_b32_e32 v0, 32, v1, vcc |
| ; SI-NEXT: v_subrev_i32_e32 v0, vcc, 24, v0 |
| ; SI-NEXT: s_waitcnt lgkmcnt(0) |
| ; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0 |
| ; SI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: v_ctlz_i8: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c |
| ; VI-NEXT: s_mov_b32 s7, 0xf000 |
| ; VI-NEXT: s_mov_b32 s6, -1 |
| ; VI-NEXT: s_mov_b32 s2, s6 |
| ; VI-NEXT: s_mov_b32 s3, s7 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 |
| ; VI-NEXT: s_waitcnt vmcnt(0) |
| ; VI-NEXT: v_ffbh_u32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 |
| ; VI-NEXT: v_cmp_ne_u16_e32 vcc, 0, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, 32, v1, vcc |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, -16, v0 |
| ; VI-NEXT: v_add_u16_e32 v0, -8, v0 |
| ; VI-NEXT: buffer_store_byte v0, off, s[4:7], 0 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; EG-LABEL: v_ctlz_i8: |
| ; EG: ; %bb.0: |
| ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: TEX 0 @6 |
| ; EG-NEXT: ALU 15, @9, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X |
| ; EG-NEXT: CF_END |
| ; EG-NEXT: PAD |
| ; EG-NEXT: Fetch clause starting at 6: |
| ; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1 |
| ; EG-NEXT: ALU clause starting at 8: |
| ; EG-NEXT: MOV * T0.X, KC0[2].Z, |
| ; EG-NEXT: ALU clause starting at 9: |
| ; EG-NEXT: FFBH_UINT * T0.W, T0.X, |
| ; EG-NEXT: CNDE_INT T0.W, T0.X, literal.x, PV.W, |
| ; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y, |
| ; EG-NEXT: 32(4.484155e-44), 3(4.203895e-45) |
| ; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x, |
| ; EG-NEXT: -24(nan), 0(0.000000e+00) |
| ; EG-NEXT: AND_INT T0.W, PV.W, literal.x, |
| ; EG-NEXT: LSHL * T1.W, T1.W, literal.y, |
| ; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45) |
| ; EG-NEXT: LSHL T0.X, PV.W, PS, |
| ; EG-NEXT: LSHL * T0.W, literal.x, PS, |
| ; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00) |
| ; EG-NEXT: MOV T0.Y, 0.0, |
| ; EG-NEXT: MOV * T0.Z, 0.0, |
| ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, |
| ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) |
| %val = load i8, i8 addrspace(1)* %valptr |
| %ctlz = call i8 @llvm.ctlz.i8(i8 %val, i1 false) nounwind readnone |
| store i8 %ctlz, i8 addrspace(1)* %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @s_ctlz_i64(i64 addrspace(1)* noalias %out, [8 x i32], i64 %val) nounwind { |
| ; SI-LABEL: s_ctlz_i64: |
| ; SI: ; %bb.0: |
| ; SI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x13 |
| ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 |
| ; SI-NEXT: s_mov_b32 s7, 0xf000 |
| ; SI-NEXT: s_mov_b32 s6, -1 |
| ; SI-NEXT: s_waitcnt lgkmcnt(0) |
| ; SI-NEXT: s_flbit_i32_b32 s0, s2 |
| ; SI-NEXT: s_flbit_i32_b32 s1, s3 |
| ; SI-NEXT: s_add_i32 s0, s0, 32 |
| ; SI-NEXT: s_or_b32 s2, s2, s3 |
| ; SI-NEXT: v_mov_b32_e32 v0, s1 |
| ; SI-NEXT: v_mov_b32_e32 v1, s0 |
| ; SI-NEXT: v_cmp_eq_u32_e64 vcc, s3, 0 |
| ; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc |
| ; SI-NEXT: v_cmp_ne_u32_e64 vcc, s2, 0 |
| ; SI-NEXT: v_cndmask_b32_e32 v0, 64, v0, vcc |
| ; SI-NEXT: v_mov_b32_e32 v1, 0 |
| ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 |
| ; SI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: s_ctlz_i64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x4c |
| ; VI-NEXT: s_mov_b32 s7, 0xf000 |
| ; VI-NEXT: s_mov_b32 s6, -1 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_flbit_i32_b32 s2, s0 |
| ; VI-NEXT: s_flbit_i32_b32 s3, s1 |
| ; VI-NEXT: s_add_i32 s2, s2, 32 |
| ; VI-NEXT: v_mov_b32_e32 v0, s3 |
| ; VI-NEXT: v_mov_b32_e32 v1, s2 |
| ; VI-NEXT: v_cmp_eq_u32_e64 vcc, s1, 0 |
| ; VI-NEXT: s_or_b32 s0, s0, s1 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc |
| ; VI-NEXT: v_cmp_ne_u32_e64 vcc, s0, 0 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, 64, v0, vcc |
| ; VI-NEXT: v_mov_b32_e32 v1, 0 |
| ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; EG-LABEL: s_ctlz_i64: |
| ; EG: ; %bb.0: |
| ; EG-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 |
| ; EG-NEXT: CF_END |
| ; EG-NEXT: PAD |
| ; EG-NEXT: ALU clause starting at 4: |
| ; EG-NEXT: FFBH_UINT * T0.W, KC0[4].W, |
| ; EG-NEXT: CNDE_INT * T0.W, KC0[4].W, literal.x, PV.W, |
| ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) |
| ; EG-NEXT: FFBH_UINT T1.W, KC0[5].X, |
| ; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x, |
| ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) |
| ; EG-NEXT: CNDE_INT T0.X, KC0[5].X, PS, PV.W, |
| ; EG-NEXT: MOV T0.Y, 0.0, |
| ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, |
| ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) |
| %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 false) |
| store i64 %ctlz, i64 addrspace(1)* %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @s_ctlz_i64_trunc(i32 addrspace(1)* noalias %out, i64 %val) nounwind { |
| ; SI-LABEL: s_ctlz_i64_trunc: |
| ; SI: ; %bb.0: |
| ; SI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb |
| ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 |
| ; SI-NEXT: s_mov_b32 s7, 0xf000 |
| ; SI-NEXT: s_mov_b32 s6, -1 |
| ; SI-NEXT: s_waitcnt lgkmcnt(0) |
| ; SI-NEXT: s_flbit_i32_b32 s0, s2 |
| ; SI-NEXT: s_flbit_i32_b32 s1, s3 |
| ; SI-NEXT: s_add_i32 s0, s0, 32 |
| ; SI-NEXT: s_or_b32 s2, s2, s3 |
| ; SI-NEXT: v_mov_b32_e32 v0, s1 |
| ; SI-NEXT: v_mov_b32_e32 v1, s0 |
| ; SI-NEXT: v_cmp_eq_u32_e64 vcc, s3, 0 |
| ; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc |
| ; SI-NEXT: v_cmp_ne_u32_e64 vcc, s2, 0 |
| ; SI-NEXT: v_cndmask_b32_e32 v0, 64, v0, vcc |
| ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 |
| ; SI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: s_ctlz_i64_trunc: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c |
| ; VI-NEXT: s_mov_b32 s7, 0xf000 |
| ; VI-NEXT: s_mov_b32 s6, -1 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: s_flbit_i32_b32 s2, s0 |
| ; VI-NEXT: s_flbit_i32_b32 s3, s1 |
| ; VI-NEXT: s_add_i32 s2, s2, 32 |
| ; VI-NEXT: v_mov_b32_e32 v0, s3 |
| ; VI-NEXT: v_mov_b32_e32 v1, s2 |
| ; VI-NEXT: v_cmp_eq_u32_e64 vcc, s1, 0 |
| ; VI-NEXT: s_or_b32 s0, s0, s1 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc |
| ; VI-NEXT: v_cmp_ne_u32_e64 vcc, s0, 0 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, 64, v0, vcc |
| ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; EG-LABEL: s_ctlz_i64_trunc: |
| ; EG: ; %bb.0: |
| ; EG-NEXT: ALU 8, @4, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 |
| ; EG-NEXT: CF_END |
| ; EG-NEXT: PAD |
| ; EG-NEXT: ALU clause starting at 4: |
| ; EG-NEXT: FFBH_UINT * T0.W, KC0[2].W, |
| ; EG-NEXT: CNDE_INT * T0.W, KC0[2].W, literal.x, PV.W, |
| ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) |
| ; EG-NEXT: FFBH_UINT T1.W, KC0[3].X, |
| ; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x, |
| ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) |
| ; EG-NEXT: CNDE_INT T0.X, KC0[3].X, PS, PV.W, |
| ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, |
| ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) |
| %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 false) |
| %trunc = trunc i64 %ctlz to i32 |
| store i32 %trunc, i32 addrspace(1)* %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @v_ctlz_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind { |
| ; SI-LABEL: v_ctlz_i64: |
| ; SI: ; %bb.0: |
| ; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9 |
| ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb |
| ; SI-NEXT: s_mov_b32 s7, 0xf000 |
| ; SI-NEXT: s_mov_b32 s6, 0 |
| ; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 |
| ; SI-NEXT: v_mov_b32_e32 v1, 0 |
| ; SI-NEXT: s_waitcnt lgkmcnt(0) |
| ; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64 |
| ; SI-NEXT: s_mov_b64 s[10:11], s[6:7] |
| ; SI-NEXT: s_waitcnt vmcnt(0) |
| ; SI-NEXT: v_ffbh_u32_e32 v4, v2 |
| ; SI-NEXT: v_ffbh_u32_e32 v5, v3 |
| ; SI-NEXT: v_or_b32_e32 v2, v2, v3 |
| ; SI-NEXT: v_add_i32_e32 v4, vcc, 32, v4 |
| ; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 |
| ; SI-NEXT: v_cndmask_b32_e32 v3, v5, v4, vcc |
| ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; SI-NEXT: v_cndmask_b32_e32 v2, 64, v3, vcc |
| ; SI-NEXT: v_mov_b32_e32 v3, v1 |
| ; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[8:11], 0 addr64 |
| ; SI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: v_ctlz_i64: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c |
| ; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 |
| ; VI-NEXT: v_mov_b32_e32 v5, 0 |
| ; VI-NEXT: v_mov_b32_e32 v1, 0 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v6, s3 |
| ; VI-NEXT: v_mov_b32_e32 v3, s1 |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v0 |
| ; VI-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc |
| ; VI-NEXT: flat_load_dwordx2 v[2:3], v[2:3] |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, s2, v0 |
| ; VI-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc |
| ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_ffbh_u32_e32 v0, v2 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, 32, v0 |
| ; VI-NEXT: v_ffbh_u32_e32 v6, v3 |
| ; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 |
| ; VI-NEXT: v_or_b32_e32 v2, v2, v3 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, 64, v0, vcc |
| ; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1] |
| ; VI-NEXT: s_endpgm |
| ; |
| ; EG-LABEL: v_ctlz_i64: |
| ; EG: ; %bb.0: |
| ; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: TEX 0 @6 |
| ; EG-NEXT: ALU 10, @11, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 |
| ; EG-NEXT: CF_END |
| ; EG-NEXT: PAD |
| ; EG-NEXT: Fetch clause starting at 6: |
| ; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1 |
| ; EG-NEXT: ALU clause starting at 8: |
| ; EG-NEXT: LSHL * T0.W, T0.X, literal.x, |
| ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) |
| ; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, |
| ; EG-NEXT: ALU clause starting at 11: |
| ; EG-NEXT: FFBH_UINT * T1.W, T0.X, |
| ; EG-NEXT: CNDE_INT * T1.W, T0.X, literal.x, PV.W, |
| ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) |
| ; EG-NEXT: FFBH_UINT T2.W, T0.Y, |
| ; EG-NEXT: ADD_INT * T1.W, PV.W, literal.x, |
| ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) |
| ; EG-NEXT: CNDE_INT T0.X, T0.Y, PS, PV.W, |
| ; EG-NEXT: MOV T0.Y, 0.0, |
| ; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W, |
| ; EG-NEXT: LSHR * T1.X, PV.W, literal.x, |
| ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) |
| %tid = call i32 @llvm.r600.read.tidig.x() |
| %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid |
| %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid |
| %val = load i64, i64 addrspace(1)* %in.gep |
| %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 false) |
| store i64 %ctlz, i64 addrspace(1)* %out.gep |
| ret void |
| } |
| |
| define amdgpu_kernel void @v_ctlz_i64_trunc(i32 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind { |
| ; SI-LABEL: v_ctlz_i64_trunc: |
| ; SI: ; %bb.0: |
| ; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9 |
| ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb |
| ; SI-NEXT: s_mov_b32 s7, 0xf000 |
| ; SI-NEXT: s_mov_b32 s6, 0 |
| ; SI-NEXT: v_lshlrev_b32_e32 v1, 3, v0 |
| ; SI-NEXT: v_mov_b32_e32 v2, 0 |
| ; SI-NEXT: s_waitcnt lgkmcnt(0) |
| ; SI-NEXT: buffer_load_dwordx2 v[3:4], v[1:2], s[4:7], 0 addr64 |
| ; SI-NEXT: v_lshlrev_b32_e32 v1, 2, v0 |
| ; SI-NEXT: s_mov_b64 s[10:11], s[6:7] |
| ; SI-NEXT: s_waitcnt vmcnt(0) |
| ; SI-NEXT: v_ffbh_u32_e32 v0, v3 |
| ; SI-NEXT: v_ffbh_u32_e32 v5, v4 |
| ; SI-NEXT: v_or_b32_e32 v3, v3, v4 |
| ; SI-NEXT: v_add_i32_e32 v0, vcc, 32, v0 |
| ; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4 |
| ; SI-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc |
| ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 |
| ; SI-NEXT: v_cndmask_b32_e32 v0, 64, v0, vcc |
| ; SI-NEXT: buffer_store_dword v0, v[1:2], s[8:11], 0 addr64 |
| ; SI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: v_ctlz_i64_trunc: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c |
| ; VI-NEXT: v_lshlrev_b32_e32 v1, 3, v0 |
| ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 |
| ; VI-NEXT: v_mov_b32_e32 v3, 0 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v4, s3 |
| ; VI-NEXT: v_mov_b32_e32 v5, s1 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v1 |
| ; VI-NEXT: v_addc_u32_e32 v1, vcc, v5, v3, vcc |
| ; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] |
| ; VI-NEXT: v_add_u32_e32 v2, vcc, s2, v2 |
| ; VI-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc |
| ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_ffbh_u32_e32 v4, v0 |
| ; VI-NEXT: v_add_u32_e32 v4, vcc, 32, v4 |
| ; VI-NEXT: v_ffbh_u32_e32 v5, v1 |
| ; VI-NEXT: v_or_b32_e32 v0, v0, v1 |
| ; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 |
| ; VI-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, 64, v1, vcc |
| ; VI-NEXT: flat_store_dword v[2:3], v0 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; EG-LABEL: v_ctlz_i64_trunc: |
| ; EG: ; %bb.0: |
| ; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: TEX 0 @6 |
| ; EG-NEXT: ALU 10, @11, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 |
| ; EG-NEXT: CF_END |
| ; EG-NEXT: PAD |
| ; EG-NEXT: Fetch clause starting at 6: |
| ; EG-NEXT: VTX_READ_64 T1.XY, T1.X, 0, #1 |
| ; EG-NEXT: ALU clause starting at 8: |
| ; EG-NEXT: LSHL * T0.W, T0.X, literal.x, |
| ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) |
| ; EG-NEXT: ADD_INT * T1.X, KC0[2].Z, PV.W, |
| ; EG-NEXT: ALU clause starting at 11: |
| ; EG-NEXT: FFBH_UINT * T0.W, T1.X, |
| ; EG-NEXT: CNDE_INT * T0.W, T1.X, literal.x, PV.W, |
| ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) |
| ; EG-NEXT: LSHL T0.Z, T0.X, literal.x, |
| ; EG-NEXT: FFBH_UINT T1.W, T1.Y, |
| ; EG-NEXT: ADD_INT * T0.W, PV.W, literal.y, |
| ; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44) |
| ; EG-NEXT: CNDE_INT T0.X, T1.Y, PS, PV.W, |
| ; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, PV.Z, |
| ; EG-NEXT: LSHR * T1.X, PV.W, literal.x, |
| ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) |
| %tid = call i32 @llvm.r600.read.tidig.x() |
| %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid |
| %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid |
| %val = load i64, i64 addrspace(1)* %in.gep |
| %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 false) |
| %trunc = trunc i64 %ctlz to i32 |
| store i32 %trunc, i32 addrspace(1)* %out.gep |
| ret void |
| } |
| |
| define amdgpu_kernel void @v_ctlz_i32_sel_eq_neg1(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { |
| ; SI-LABEL: v_ctlz_i32_sel_eq_neg1: |
| ; SI: ; %bb.0: |
| ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 |
| ; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb |
| ; SI-NEXT: s_mov_b32 s7, 0xf000 |
| ; SI-NEXT: s_mov_b32 s10, 0 |
| ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 |
| ; SI-NEXT: v_mov_b32_e32 v1, 0 |
| ; SI-NEXT: s_mov_b32 s11, s7 |
| ; SI-NEXT: s_waitcnt lgkmcnt(0) |
| ; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64 |
| ; SI-NEXT: s_mov_b32 s6, -1 |
| ; SI-NEXT: s_waitcnt vmcnt(0) |
| ; SI-NEXT: v_ffbh_u32_e32 v0, v0 |
| ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 |
| ; SI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: v_ctlz_i32_sel_eq_neg1: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c |
| ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 |
| ; VI-NEXT: s_mov_b32 s7, 0xf000 |
| ; VI-NEXT: s_mov_b32 s6, -1 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v1, s1 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 |
| ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; VI-NEXT: flat_load_dword v0, v[0:1] |
| ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_ffbh_u32_e32 v0, v0 |
| ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; EG-LABEL: v_ctlz_i32_sel_eq_neg1: |
| ; EG: ; %bb.0: |
| ; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: TEX 0 @6 |
| ; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 |
| ; EG-NEXT: CF_END |
| ; EG-NEXT: PAD |
| ; EG-NEXT: Fetch clause starting at 6: |
| ; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 |
| ; EG-NEXT: ALU clause starting at 8: |
| ; EG-NEXT: LSHL * T0.W, T0.X, literal.x, |
| ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) |
| ; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, |
| ; EG-NEXT: ALU clause starting at 11: |
| ; EG-NEXT: FFBH_UINT * T0.W, T0.X, |
| ; EG-NEXT: CNDE_INT * T0.W, T0.X, literal.x, PV.W, |
| ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) |
| ; EG-NEXT: CNDE_INT T0.X, T0.X, literal.x, PV.W, |
| ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, |
| ; EG-NEXT: -1(nan), 2(2.802597e-45) |
| %tid = call i32 @llvm.r600.read.tidig.x() |
| %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid |
| %val = load i32, i32 addrspace(1)* %in.gep |
| %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 false) nounwind readnone |
| %cmp = icmp eq i32 %val, 0 |
| %sel = select i1 %cmp, i32 -1, i32 %ctlz |
| store i32 %sel, i32 addrspace(1)* %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @v_ctlz_i32_sel_ne_neg1(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { |
| ; SI-LABEL: v_ctlz_i32_sel_ne_neg1: |
| ; SI: ; %bb.0: |
| ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 |
| ; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb |
| ; SI-NEXT: s_mov_b32 s7, 0xf000 |
| ; SI-NEXT: s_mov_b32 s10, 0 |
| ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 |
| ; SI-NEXT: v_mov_b32_e32 v1, 0 |
| ; SI-NEXT: s_mov_b32 s11, s7 |
| ; SI-NEXT: s_waitcnt lgkmcnt(0) |
| ; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64 |
| ; SI-NEXT: s_mov_b32 s6, -1 |
| ; SI-NEXT: s_waitcnt vmcnt(0) |
| ; SI-NEXT: v_ffbh_u32_e32 v0, v0 |
| ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 |
| ; SI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: v_ctlz_i32_sel_ne_neg1: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c |
| ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 |
| ; VI-NEXT: s_mov_b32 s7, 0xf000 |
| ; VI-NEXT: s_mov_b32 s6, -1 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v1, s1 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 |
| ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; VI-NEXT: flat_load_dword v0, v[0:1] |
| ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_ffbh_u32_e32 v0, v0 |
| ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; EG-LABEL: v_ctlz_i32_sel_ne_neg1: |
| ; EG: ; %bb.0: |
| ; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: TEX 0 @6 |
| ; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 |
| ; EG-NEXT: CF_END |
| ; EG-NEXT: PAD |
| ; EG-NEXT: Fetch clause starting at 6: |
| ; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 |
| ; EG-NEXT: ALU clause starting at 8: |
| ; EG-NEXT: LSHL * T0.W, T0.X, literal.x, |
| ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) |
| ; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, |
| ; EG-NEXT: ALU clause starting at 11: |
| ; EG-NEXT: FFBH_UINT * T0.W, T0.X, |
| ; EG-NEXT: CNDE_INT * T0.W, T0.X, literal.x, PV.W, |
| ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) |
| ; EG-NEXT: CNDE_INT T0.X, T0.X, literal.x, PV.W, |
| ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, |
| ; EG-NEXT: -1(nan), 2(2.802597e-45) |
| %tid = call i32 @llvm.r600.read.tidig.x() |
| %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid |
| %val = load i32, i32 addrspace(1)* %in.gep |
| %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 false) nounwind readnone |
| %cmp = icmp ne i32 %val, 0 |
| %sel = select i1 %cmp, i32 %ctlz, i32 -1 |
| store i32 %sel, i32 addrspace(1)* %out |
| ret void |
| } |
| |
| ; TODO: Should be able to eliminate select here as well. |
| define amdgpu_kernel void @v_ctlz_i32_sel_eq_bitwidth(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { |
| ; SI-LABEL: v_ctlz_i32_sel_eq_bitwidth: |
| ; SI: ; %bb.0: |
| ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 |
| ; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb |
| ; SI-NEXT: s_mov_b32 s7, 0xf000 |
| ; SI-NEXT: s_mov_b32 s10, 0 |
| ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 |
| ; SI-NEXT: v_mov_b32_e32 v1, 0 |
| ; SI-NEXT: s_mov_b32 s11, s7 |
| ; SI-NEXT: s_waitcnt lgkmcnt(0) |
| ; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64 |
| ; SI-NEXT: s_mov_b32 s6, -1 |
| ; SI-NEXT: s_waitcnt vmcnt(0) |
| ; SI-NEXT: v_ffbh_u32_e32 v1, v0 |
| ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 |
| ; SI-NEXT: v_cndmask_b32_e32 v0, 32, v1, vcc |
| ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 32, v0 |
| ; SI-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc |
| ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 |
| ; SI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: v_ctlz_i32_sel_eq_bitwidth: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c |
| ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 |
| ; VI-NEXT: s_mov_b32 s7, 0xf000 |
| ; VI-NEXT: s_mov_b32 s6, -1 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v1, s1 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 |
| ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; VI-NEXT: flat_load_dword v0, v[0:1] |
| ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_ffbh_u32_e32 v1, v0 |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, 32, v1, vcc |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 32, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc |
| ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; EG-LABEL: v_ctlz_i32_sel_eq_bitwidth: |
| ; EG: ; %bb.0: |
| ; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: TEX 0 @6 |
| ; EG-NEXT: ALU 7, @11, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 |
| ; EG-NEXT: CF_END |
| ; EG-NEXT: PAD |
| ; EG-NEXT: Fetch clause starting at 6: |
| ; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 |
| ; EG-NEXT: ALU clause starting at 8: |
| ; EG-NEXT: LSHL * T0.W, T0.X, literal.x, |
| ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) |
| ; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, |
| ; EG-NEXT: ALU clause starting at 11: |
| ; EG-NEXT: FFBH_UINT * T0.W, T0.X, |
| ; EG-NEXT: CNDE_INT * T0.W, T0.X, literal.x, PV.W, |
| ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) |
| ; EG-NEXT: SETE_INT * T1.W, PV.W, literal.x, |
| ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) |
| ; EG-NEXT: CNDE_INT T0.X, PV.W, T0.W, literal.x, |
| ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, |
| ; EG-NEXT: -1(nan), 2(2.802597e-45) |
| %tid = call i32 @llvm.r600.read.tidig.x() |
| %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid |
| %val = load i32, i32 addrspace(1)* %in.gep |
| %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 false) nounwind readnone |
| %cmp = icmp eq i32 %ctlz, 32 |
| %sel = select i1 %cmp, i32 -1, i32 %ctlz |
| store i32 %sel, i32 addrspace(1)* %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @v_ctlz_i32_sel_ne_bitwidth(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { |
| ; SI-LABEL: v_ctlz_i32_sel_ne_bitwidth: |
| ; SI: ; %bb.0: |
| ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 |
| ; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb |
| ; SI-NEXT: s_mov_b32 s7, 0xf000 |
| ; SI-NEXT: s_mov_b32 s10, 0 |
| ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 |
| ; SI-NEXT: v_mov_b32_e32 v1, 0 |
| ; SI-NEXT: s_mov_b32 s11, s7 |
| ; SI-NEXT: s_waitcnt lgkmcnt(0) |
| ; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64 |
| ; SI-NEXT: s_mov_b32 s6, -1 |
| ; SI-NEXT: s_waitcnt vmcnt(0) |
| ; SI-NEXT: v_ffbh_u32_e32 v1, v0 |
| ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 |
| ; SI-NEXT: v_cndmask_b32_e32 v0, 32, v1, vcc |
| ; SI-NEXT: v_cmp_ne_u32_e32 vcc, 32, v0 |
| ; SI-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc |
| ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 |
| ; SI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: v_ctlz_i32_sel_ne_bitwidth: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c |
| ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 |
| ; VI-NEXT: s_mov_b32 s7, 0xf000 |
| ; VI-NEXT: s_mov_b32 s6, -1 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v1, s1 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 |
| ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; VI-NEXT: flat_load_dword v0, v[0:1] |
| ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_ffbh_u32_e32 v1, v0 |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, 32, v1, vcc |
| ; VI-NEXT: v_cmp_ne_u32_e32 vcc, 32, v0 |
| ; VI-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc |
| ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; EG-LABEL: v_ctlz_i32_sel_ne_bitwidth: |
| ; EG: ; %bb.0: |
| ; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: TEX 0 @6 |
| ; EG-NEXT: ALU 7, @11, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 |
| ; EG-NEXT: CF_END |
| ; EG-NEXT: PAD |
| ; EG-NEXT: Fetch clause starting at 6: |
| ; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1 |
| ; EG-NEXT: ALU clause starting at 8: |
| ; EG-NEXT: LSHL * T0.W, T0.X, literal.x, |
| ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) |
| ; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W, |
| ; EG-NEXT: ALU clause starting at 11: |
| ; EG-NEXT: FFBH_UINT * T0.W, T0.X, |
| ; EG-NEXT: CNDE_INT * T0.W, T0.X, literal.x, PV.W, |
| ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) |
| ; EG-NEXT: SETNE_INT * T1.W, PV.W, literal.x, |
| ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) |
| ; EG-NEXT: CNDE_INT T0.X, PV.W, literal.x, T0.W, |
| ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, |
| ; EG-NEXT: -1(nan), 2(2.802597e-45) |
| %tid = call i32 @llvm.r600.read.tidig.x() |
| %in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid |
| %val = load i32, i32 addrspace(1)* %in.gep |
| %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 false) nounwind readnone |
| %cmp = icmp ne i32 %ctlz, 32 |
| %sel = select i1 %cmp, i32 %ctlz, i32 -1 |
| store i32 %sel, i32 addrspace(1)* %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @v_ctlz_i8_sel_eq_neg1(i8 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %valptr) nounwind { |
| ; SI-LABEL: v_ctlz_i8_sel_eq_neg1: |
| ; SI: ; %bb.0: |
| ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 |
| ; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb |
| ; SI-NEXT: s_mov_b32 s7, 0xf000 |
| ; SI-NEXT: v_mov_b32_e32 v1, 0 |
| ; SI-NEXT: s_mov_b32 s10, 0 |
| ; SI-NEXT: s_mov_b32 s11, s7 |
| ; SI-NEXT: s_waitcnt lgkmcnt(0) |
| ; SI-NEXT: buffer_load_ubyte v0, v[0:1], s[8:11], 0 addr64 |
| ; SI-NEXT: s_mov_b32 s6, -1 |
| ; SI-NEXT: s_waitcnt vmcnt(0) |
| ; SI-NEXT: v_ffbh_u32_e32 v0, v0 |
| ; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0 |
| ; SI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: v_ctlz_i8_sel_eq_neg1: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c |
| ; VI-NEXT: s_mov_b32 s7, 0xf000 |
| ; VI-NEXT: s_mov_b32 s6, -1 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v1, s1 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 |
| ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; VI-NEXT: flat_load_ubyte v0, v[0:1] |
| ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_ffbh_u32_e32 v0, v0 |
| ; VI-NEXT: buffer_store_byte v0, off, s[4:7], 0 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; EG-LABEL: v_ctlz_i8_sel_eq_neg1: |
| ; EG: ; %bb.0: |
| ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: TEX 0 @6 |
| ; EG-NEXT: ALU 12, @9, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X |
| ; EG-NEXT: CF_END |
| ; EG-NEXT: PAD |
| ; EG-NEXT: Fetch clause starting at 6: |
| ; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1 |
| ; EG-NEXT: ALU clause starting at 8: |
| ; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, T0.X, |
| ; EG-NEXT: ALU clause starting at 9: |
| ; EG-NEXT: FFBH_UINT T0.W, T0.X, |
| ; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x, |
| ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) |
| ; EG-NEXT: AND_INT T0.W, PV.W, literal.x, |
| ; EG-NEXT: LSHL * T1.W, PS, literal.y, |
| ; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45) |
| ; EG-NEXT: LSHL T0.X, PV.W, PS, |
| ; EG-NEXT: LSHL * T0.W, literal.x, PS, |
| ; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00) |
| ; EG-NEXT: MOV T0.Y, 0.0, |
| ; EG-NEXT: MOV * T0.Z, 0.0, |
| ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, |
| ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) |
| %tid = call i32 @llvm.r600.read.tidig.x() |
| %valptr.gep = getelementptr i8, i8 addrspace(1)* %valptr, i32 %tid |
| %val = load i8, i8 addrspace(1)* %valptr.gep |
| %ctlz = call i8 @llvm.ctlz.i8(i8 %val, i1 false) nounwind readnone |
| %cmp = icmp eq i8 %val, 0 |
| %sel = select i1 %cmp, i8 -1, i8 %ctlz |
| store i8 %sel, i8 addrspace(1)* %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @v_ctlz_i16_sel_eq_neg1(i16 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %valptr) nounwind { |
| ; SI-LABEL: v_ctlz_i16_sel_eq_neg1: |
| ; SI: ; %bb.0: |
| ; SI-NEXT: s_mov_b32 s3, 0xf000 |
| ; SI-NEXT: s_mov_b32 s2, -1 |
| ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb |
| ; SI-NEXT: s_mov_b32 s6, s2 |
| ; SI-NEXT: s_mov_b32 s7, s3 |
| ; SI-NEXT: s_waitcnt lgkmcnt(0) |
| ; SI-NEXT: buffer_load_ushort v0, off, s[4:7], 0 |
| ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 |
| ; SI-NEXT: s_waitcnt vmcnt(0) |
| ; SI-NEXT: v_ffbh_u32_e32 v0, v0 |
| ; SI-NEXT: s_waitcnt lgkmcnt(0) |
| ; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 |
| ; SI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: v_ctlz_i16_sel_eq_neg1: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c |
| ; VI-NEXT: s_mov_b32 s7, 0xf000 |
| ; VI-NEXT: s_mov_b32 s6, -1 |
| ; VI-NEXT: s_mov_b32 s2, s6 |
| ; VI-NEXT: s_mov_b32 s3, s7 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: buffer_load_ushort v0, off, s[0:3], 0 |
| ; VI-NEXT: s_waitcnt vmcnt(0) |
| ; VI-NEXT: v_ffbh_u32_e32 v1, v0 |
| ; VI-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v0 |
| ; VI-NEXT: v_cndmask_b32_e64 v0, 32, v1, s[0:1] |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, -16, v0 |
| ; VI-NEXT: v_mov_b32_e32 v1, 0xffff |
| ; VI-NEXT: v_cndmask_b32_e64 v0, v1, v0, s[0:1] |
| ; VI-NEXT: buffer_store_short v0, off, s[4:7], 0 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; EG-LABEL: v_ctlz_i16_sel_eq_neg1: |
| ; EG: ; %bb.0: |
| ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: TEX 0 @6 |
| ; EG-NEXT: ALU 12, @9, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X |
| ; EG-NEXT: CF_END |
| ; EG-NEXT: PAD |
| ; EG-NEXT: Fetch clause starting at 6: |
| ; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #1 |
| ; EG-NEXT: ALU clause starting at 8: |
| ; EG-NEXT: MOV * T0.X, KC0[2].Z, |
| ; EG-NEXT: ALU clause starting at 9: |
| ; EG-NEXT: FFBH_UINT T0.W, T0.X, |
| ; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x, |
| ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) |
| ; EG-NEXT: AND_INT T0.W, PV.W, literal.x, |
| ; EG-NEXT: LSHL * T1.W, PS, literal.y, |
| ; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45) |
| ; EG-NEXT: LSHL T0.X, PV.W, PS, |
| ; EG-NEXT: LSHL * T0.W, literal.x, PS, |
| ; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00) |
| ; EG-NEXT: MOV T0.Y, 0.0, |
| ; EG-NEXT: MOV * T0.Z, 0.0, |
| ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, |
| ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) |
| %val = load i16, i16 addrspace(1)* %valptr |
| %ctlz = call i16 @llvm.ctlz.i16(i16 %val, i1 false) nounwind readnone |
| %cmp = icmp eq i16 %val, 0 |
| %sel = select i1 %cmp, i16 -1, i16 %ctlz |
| store i16 %sel, i16 addrspace(1)* %out |
| ret void |
| } |
| |
| ; FIXME: Need to handle non-uniform case for function below (load without gep). |
| define amdgpu_kernel void @v_ctlz_i7_sel_eq_neg1(i7 addrspace(1)* noalias %out, i7 addrspace(1)* noalias %valptr) nounwind { |
| ; SI-LABEL: v_ctlz_i7_sel_eq_neg1: |
| ; SI: ; %bb.0: |
| ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 |
| ; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb |
| ; SI-NEXT: s_mov_b32 s7, 0xf000 |
| ; SI-NEXT: v_mov_b32_e32 v1, 0 |
| ; SI-NEXT: s_mov_b32 s10, 0 |
| ; SI-NEXT: s_mov_b32 s11, s7 |
| ; SI-NEXT: s_waitcnt lgkmcnt(0) |
| ; SI-NEXT: buffer_load_ubyte v0, v[0:1], s[8:11], 0 addr64 |
| ; SI-NEXT: s_mov_b32 s6, -1 |
| ; SI-NEXT: s_waitcnt vmcnt(0) |
| ; SI-NEXT: v_ffbh_u32_e32 v0, v0 |
| ; SI-NEXT: v_and_b32_e32 v0, 0x7f, v0 |
| ; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0 |
| ; SI-NEXT: s_endpgm |
| ; |
| ; VI-LABEL: v_ctlz_i7_sel_eq_neg1: |
| ; VI: ; %bb.0: |
| ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 |
| ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c |
| ; VI-NEXT: s_mov_b32 s7, 0xf000 |
| ; VI-NEXT: s_mov_b32 s6, -1 |
| ; VI-NEXT: s_waitcnt lgkmcnt(0) |
| ; VI-NEXT: v_mov_b32_e32 v1, s1 |
| ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0 |
| ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; VI-NEXT: flat_load_ubyte v0, v[0:1] |
| ; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) |
| ; VI-NEXT: v_ffbh_u32_e32 v0, v0 |
| ; VI-NEXT: v_and_b32_e32 v0, 0x7f, v0 |
| ; VI-NEXT: buffer_store_byte v0, off, s[4:7], 0 |
| ; VI-NEXT: s_endpgm |
| ; |
| ; EG-LABEL: v_ctlz_i7_sel_eq_neg1: |
| ; EG: ; %bb.0: |
| ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: TEX 0 @6 |
| ; EG-NEXT: ALU 12, @9, KC0[CB0:0-32], KC1[] |
| ; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X |
| ; EG-NEXT: CF_END |
| ; EG-NEXT: PAD |
| ; EG-NEXT: Fetch clause starting at 6: |
| ; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1 |
| ; EG-NEXT: ALU clause starting at 8: |
| ; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, T0.X, |
| ; EG-NEXT: ALU clause starting at 9: |
| ; EG-NEXT: FFBH_UINT T0.W, T0.X, |
| ; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x, |
| ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00) |
| ; EG-NEXT: AND_INT T0.W, PV.W, literal.x, |
| ; EG-NEXT: LSHL * T1.W, PS, literal.y, |
| ; EG-NEXT: 127(1.779649e-43), 3(4.203895e-45) |
| ; EG-NEXT: LSHL T0.X, PV.W, PS, |
| ; EG-NEXT: LSHL * T0.W, literal.x, PS, |
| ; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00) |
| ; EG-NEXT: MOV T0.Y, 0.0, |
| ; EG-NEXT: MOV * T0.Z, 0.0, |
| ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, |
| ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) |
| %tid = call i32 @llvm.r600.read.tidig.x() |
| %valptr.gep = getelementptr i7, i7 addrspace(1)* %valptr, i32 %tid |
| %val = load i7, i7 addrspace(1)* %valptr.gep |
| %ctlz = call i7 @llvm.ctlz.i7(i7 %val, i1 false) nounwind readnone |
| %cmp = icmp eq i7 %val, 0 |
| %sel = select i1 %cmp, i7 -1, i7 %ctlz |
| store i7 %sel, i7 addrspace(1)* %out |
| ret void |
| } |