test/CodeGen/Thumb2/LowOverheadLoops/massive.mir

# RUN: llc -mtriple=armv8.1m.main -mattr=+lob -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s
# CHECK: for.body:
# CHECK-NOT: t2DLS
# CHECK-NOT: t2LEUpdate

--- |  
  define dso_local arm_aapcscc void @massive(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) local_unnamed_addr {
  entry:
    %cmp8 = icmp eq i32 %N, 0
    br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader
  
  for.body.preheader:                               ; preds = %entry
    %scevgep = getelementptr i32, i32* %a, i32 -1
    %scevgep4 = getelementptr i32, i32* %c, i32 -1
    %scevgep8 = getelementptr i32, i32* %b, i32 -1
    call void @llvm.set.loop.iterations.i32(i32 %N)
    br label %for.body
  
  for.cond.cleanup:                                 ; preds = %for.body, %entry
    ret void
  
  for.body:                                         ; preds = %for.body, %for.body.preheader
    %lsr.iv9 = phi i32* [ %scevgep8, %for.body.preheader ], [ %scevgep10, %for.body ]
    %lsr.iv5 = phi i32* [ %scevgep4, %for.body.preheader ], [ %scevgep6, %for.body ]
    %lsr.iv1 = phi i32* [ %scevgep, %for.body.preheader ], [ %scevgep2, %for.body ]
    %0 = phi i32 [ %N, %for.body.preheader ], [ %3, %for.body ]
    %size = call i32 @llvm.arm.space(i32 4096, i32 undef)
    %scevgep1 = getelementptr i32, i32* %lsr.iv9, i32 1
    %1 = load i32, i32* %scevgep1, align 4, !tbaa !3
    %scevgep5 = getelementptr i32, i32* %lsr.iv5, i32 1
    %2 = load i32, i32* %scevgep5, align 4, !tbaa !3
    %mul = mul nsw i32 %2, %1
    %scevgep9 = getelementptr i32, i32* %lsr.iv1, i32 1
    store i32 %mul, i32* %scevgep9, align 4, !tbaa !3
    %scevgep2 = getelementptr i32, i32* %lsr.iv1, i32 1
    %scevgep6 = getelementptr i32, i32* %lsr.iv5, i32 1
    %scevgep10 = getelementptr i32, i32* %lsr.iv9, i32 1
    %3 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)
    %4 = icmp ne i32 %3, 0
    br i1 %4, label %for.body, label %for.cond.cleanup
  }
  
  ; Function Attrs: nounwind
  declare i32 @llvm.arm.space(i32 immarg, i32) #0

  ; Function Attrs: noduplicate nounwind
  declare void @llvm.set.loop.iterations.i32(i32) #1
  
  ; Function Attrs: noduplicate nounwind
  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1
  
  attributes #0 = { nounwind }
  attributes #1 = { noduplicate nounwind }
  
  !llvm.module.flags = !{!0, !1}
  !llvm.ident = !{!2}
  
  !0 = !{i32 1, !"wchar_size", i32 4}
  !1 = !{i32 1, !"min_enum_size", i32 4}
  !2 = !{!"clang version 9.0.0 (http://llvm.org/git/clang.git a9c7c0fc5d468f3d18a5c6beb697ab0d5be2ff4c) (http://llvm.org/git/llvm.git f34bff0c141a04a5182d57e2cfb1e4bc582c81b0)"}
  !3 = !{!4, !4, i64 0}
  !4 = !{!"int", !5, i64 0}
  !5 = !{!"omnipotent char", !6, i64 0}
  !6 = !{!"Simple C/C++ TBAA"}

...
---
name:            massive
alignment:       1
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: false
hasWinCFI:       false
registers:       []
liveins:
  - { reg: '$r0', virtual-reg: '' }
  - { reg: '$r1', virtual-reg: '' }
  - { reg: '$r2', virtual-reg: '' }
  - { reg: '$r3', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       8
  offsetAdjustment: 0
  maxAlignment:    4
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  cvBytesOfCalleeSavedRegisters: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:      []
stack:
  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 
      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 
      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites:       []
constants:       []
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    successors: %bb.1(0x80000000)
  
    frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
    frame-setup CFI_INSTRUCTION def_cfa_offset 8
    frame-setup CFI_INSTRUCTION offset $lr, -4
    frame-setup CFI_INSTRUCTION offset $r7, -8
    tCMPi8 $r3, 0, 14, $noreg, implicit-def $cpsr
    t2IT 0, 8, implicit-def $itstate
    tPOP_RET 0, killed $cpsr, def $r7, def $pc, implicit killed $itstate
    renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg
    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
    renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14, $noreg
    $lr = tMOVr $r3, 14, $noreg
    t2DoLoopStart killed $r3
  
  bb.1.for.body:
    successors: %bb.1(0x7c000000), %bb.2(0x04000000)
  
    dead renamable $r3 = SPACE 4096, undef renamable $r0
    renamable $r12, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep1, !tbaa !3)
    renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14, $noreg :: (load 4 from %ir.scevgep5, !tbaa !3)
    renamable $r3 = nsw t2MUL killed renamable $r3, killed renamable $r12, 14, $noreg
    early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep9, !tbaa !3)
    renamable $lr = t2LoopDec killed renamable $lr, 1
    t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
    tB %bb.2, 14, $noreg
  
  bb.2.for.cond.cleanup:
    tPOP_RET 14, $noreg, def $r7, def $pc

...