[TargetLowering] avoid miscompile in setcc transform (PR40657)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353615 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 484dbff..b933f03 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -3074,7 +3074,9 @@
return DAG.getSetCC(dl, VT, N0.getOperand(0),
DAG.getConstant(0, dl, N0.getValueType()),
Cond);
- if (N0.getNode()->hasOneUse()) {
+ // The shift is not valid if this is a bool (i1).
+ // TODO: This transform needs evidence to justify its existence.
+ if (N0.getNode()->hasOneUse() && OpVT.getScalarSizeInBits() != 1) {
assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
auto &DL = DAG.getDataLayout();
// (Z-X) == X --> Z == X<<1
diff --git a/test/CodeGen/X86/setcc-combine.ll b/test/CodeGen/X86/setcc-combine.ll
index d7f0a26..749d99b 100644
--- a/test/CodeGen/X86/setcc-combine.ll
+++ b/test/CodeGen/X86/setcc-combine.ll
@@ -262,12 +262,15 @@
ret void
}
-; FIXME: This should not get folded to 0.
+; This should not get folded to 0.
define i64 @PR40657(i8 %var2, i8 %var9) {
; CHECK-LABEL: PR40657:
; CHECK: # %bb.0:
-; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: notb %sil
+; CHECK-NEXT: addb %dil, %sil
+; CHECK-NEXT: movzbl %sil, %eax
+; CHECK-NEXT: andl $1, %eax
; CHECK-NEXT: retq
%var6 = trunc i8 %var9 to i1
%var7 = trunc i8 175 to i1
