commit af74a3fbda42dd0841b9184bc386b4bd7b264689
author Kai Luo <lkail@cn.ibm.com> Wed Jun 26 05:25:16 2019 +0000
committer Kai Luo <lkail@cn.ibm.com> Wed Jun 26 05:25:16 2019 +0000
tree 0331ac18bd2e6086d2de3428f69e30ef32f86be0
parent 2d7ed2481d6c65bf20983414d1fbcf8d3a021bab

[PowerPC] Fixed missing change flag of emitRLDICWhenLoweringJumpTables

PPCMIPeephole::emitRLDICWhenLoweringJumpTables should return a bool
value to indicate optimization is conducted or not.

Differential Revision: https://reviews.llvm.org/D63801

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364383 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PowerPC/PPCMIPeephole.cpp

diff --git a/lib/Target/PowerPC/PPCMIPeephole.cpp b/lib/Target/PowerPC/PPCMIPeephole.cpp
index 6e693bd..54f8f77 100644
--- a/lib/Target/PowerPC/PPCMIPeephole.cpp
+++ b/lib/Target/PowerPC/PPCMIPeephole.cpp
@@ -94,7 +94,7 @@
   // Perform peepholes.
   bool eliminateRedundantCompare(void);
   bool eliminateRedundantTOCSaves(std::map<MachineInstr *, bool> &TOCSaves);
-  void emitRLDICWhenLoweringJumpTables(MachineInstr &MI);
+  bool emitRLDICWhenLoweringJumpTables(MachineInstr &MI);
   void UpdateTOCSaves(std::map<MachineInstr *, bool> &TOCSaves,
                       MachineInstr *MI);
 
@@ -761,7 +761,7 @@
         break;
       }
       case PPC::RLDICR: {
-        emitRLDICWhenLoweringJumpTables(MI);
+        Simplified = emitRLDICWhenLoweringJumpTables(MI);
         break;
       }
       }
@@ -1284,17 +1284,17 @@
 // We miss the opportunity to emit an RLDIC when lowering jump tables
 // since ISEL sees only a single basic block. When selecting, the clear
 // and shift left will be in different blocks.
-void PPCMIPeephole::emitRLDICWhenLoweringJumpTables(MachineInstr &MI) {
+bool PPCMIPeephole::emitRLDICWhenLoweringJumpTables(MachineInstr &MI) {
   if (MI.getOpcode() != PPC::RLDICR)
-    return;
+    return false;
 
   unsigned SrcReg = MI.getOperand(1).getReg();
   if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
-    return;
+    return false;
 
   MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
   if (SrcMI->getOpcode() != PPC::RLDICL)
-    return;
+    return false;
 
   MachineOperand MOpSHSrc = SrcMI->getOperand(2);
   MachineOperand MOpMBSrc = SrcMI->getOperand(3);
@@ -1302,7 +1302,7 @@
   MachineOperand MOpMEMI = MI.getOperand(3);
   if (!(MOpSHSrc.isImm() && MOpMBSrc.isImm() && MOpSHMI.isImm() &&
         MOpMEMI.isImm()))
-    return;
+    return false;
 
   uint64_t SHSrc = MOpSHSrc.getImm();
   uint64_t MBSrc = MOpMBSrc.getImm();
@@ -1311,7 +1311,7 @@
   uint64_t NewSH = SHSrc + SHMI;
   uint64_t NewMB = MBSrc - SHMI;
   if (NewMB > 63 || NewSH > 63)
-    return;
+    return false;
 
   // The bits cleared with RLDICL are [0, MBSrc).
   // The bits cleared with RLDICR are (MEMI, 63].
@@ -1320,7 +1320,7 @@
   //
   // The bits cleared with RLDIC are [0, NewMB) and (63-NewSH, 63].
   if ((63 - NewSH) != MEMI)
-    return;
+    return false;
 
   LLVM_DEBUG(dbgs() << "Converting pair: ");
   LLVM_DEBUG(SrcMI->dump());
@@ -1334,6 +1334,7 @@
   LLVM_DEBUG(dbgs() << "To: ");
   LLVM_DEBUG(MI.dump());
   NumRotatesCollapsed++;
+  return true;
 }
 
 } // end default namespace