commit ac0d6fee07540817c2e71f4b96280dcc7221be65
author Alex Bradbury <asb@lowrisc.org> Thu Mar 14 08:31:35 2019 +0000
committer Alex Bradbury <asb@lowrisc.org> Thu Mar 14 08:31:35 2019 +0000
tree 2fdf101c3c9f87003cad100b8d7fdf2faa483944
parent b216751ea8fcedf2ea7db2390ce6cf5862bc0428

[RISCV] Fix rL356123

The wrong version of the patch was committed. This fixes typos that broke the build.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356124 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/RISCV/RISCVRegisterInfo.cpp

diff --git a/lib/Target/RISCV/RISCVRegisterInfo.cpp b/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 0beb166..6e0aa10 100644
--- a/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -36,7 +36,7 @@
   if (MF->getFunction().hasFnAttribute("interrupt")) {
     if (Subtarget.hasStdExtD())
       return CSR_XLEN_F64_Interrupt_SaveList;
-    if (Subtarget..hasStdExtF())
+    if (Subtarget.hasStdExtF())
       return CSR_XLEN_F32_Interrupt_SaveList;
     return CSR_Interrupt_SaveList;
   }
@@ -119,7 +119,7 @@
 const uint32_t *
 RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
                                         CallingConv::ID /*CC*/) const {
-  auto &Subtarget = MF->getSubtarget<RISCVSubtarget>();
+  auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
   if (MF.getFunction().hasFnAttribute("interrupt")) {
     if (Subtarget.hasStdExtD())
       return CSR_XLEN_F64_Interrupt_RegMask;