commit a5a5e44a42e3dbb97059440c88e857de2b0a679a
author Evandro Menezes <e.menezes@samsung.com> Tue Dec 18 23:19:55 2018 +0000
committer Evandro Menezes <e.menezes@samsung.com> Tue Dec 18 23:19:55 2018 +0000
tree 71de23602e54b60fd39a953eeb547866c8bd6ca5
parent ab30375a3908b6d43f17344fbdb901b4d251f738

[AArch64] Fix instructions order (NFC)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349568 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/AArch64/AArch64SchedExynosM1.td

diff --git a/lib/Target/AArch64/AArch64SchedExynosM1.td b/lib/Target/AArch64/AArch64SchedExynosM1.td
index 62a4650..7f1c2d4 100644
--- a/lib/Target/AArch64/AArch64SchedExynosM1.td
+++ b/lib/Target/AArch64/AArch64SchedExynosM1.td
@@ -440,14 +440,14 @@
 // Miscellaneous instructions.
 
 // Load instructions.
-def : InstRW<[M1WriteLC,
-              ReadAdrBase], (instregex "^LDR(BB|HH|SBW|SBX|SHW|SWX|SW|W|X)roW")>;
-def : InstRW<[M1WriteL5,
-              ReadAdrBase], (instregex "^LDR(BB|HH|SBW|SBX|SHW|SWX|SW|W|X)roX")>;
 def : InstRW<[M1WriteLB,
               WriteLDHi,
               WriteAdr],    (instregex "^LDP(SW|W|X)(post|pre)")>;
 def : InstRW<[M1WriteLC,
+              ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>;
+def : InstRW<[M1WriteL5,
+              ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>;
+def : InstRW<[M1WriteLC,
               ReadAdrBase], (instrs PRFMroW)>;
 def : InstRW<[M1WriteL5,
               ReadAdrBase], (instrs PRFMroX)>;