commit a568d027b025fb4c0e22298e9c54b537b9f53daa
author Alex Bradbury <asb@lowrisc.org> Thu Feb 14 13:09:54 2019 +0000
committer Alex Bradbury <asb@lowrisc.org> Thu Feb 14 13:09:54 2019 +0000
tree e697a7fa8a26b564ab4f962ef7ec7112cc633344
parent c5767506b555781e756cc395195850f4310fa5fc

[RISCV][NFC] Add RV64I CHECK lines to inline-asm.ll test


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354028 91177308-0d34-0410-b5e6-96231b3b80d8

test/CodeGen/RISCV/inline-asm.ll

diff --git a/test/CodeGen/RISCV/inline-asm.ll b/test/CodeGen/RISCV/inline-asm.ll
index a16375b..f17852c 100644
--- a/test/CodeGen/RISCV/inline-asm.ll
+++ b/test/CodeGen/RISCV/inline-asm.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64I %s
 
 @gi = external global i32
 
@@ -13,6 +15,15 @@
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: constraint_r:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, %hi(gi)
+; RV64I-NEXT:    lwu a1, %lo(gi)(a1)
+; RV64I-NEXT:    #APP
+; RV64I-NEXT:    add a0, a0, a1
+; RV64I-NEXT:    #NO_APP
+; RV64I-NEXT:    ret
   %1 = load i32, i32* @gi
   %2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 %a, i32 %1)
   ret i32 %2
@@ -25,6 +36,13 @@
 ; RV32I-NEXT:    addi a0, a0, 113
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: constraint_i:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    #APP
+; RV64I-NEXT:    addi a0, a0, 113
+; RV64I-NEXT:    #NO_APP
+; RV64I-NEXT:    ret
   %1 = load i32, i32* @gi
   %2 = tail call i32 asm "addi $0, $1, $2", "=r,r,i"(i32 %a, i32 113)
   ret i32 %2
@@ -36,6 +54,12 @@
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: constraint_m:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    #APP
+; RV64I-NEXT:    #NO_APP
+; RV64I-NEXT:    ret
   call void asm sideeffect "", "=*m"(i32* %a)
   ret void
 }
@@ -47,6 +71,13 @@
 ; RV32I-NEXT:    lw a0, 0(a0)
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: constraint_m2:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    #APP
+; RV64I-NEXT:    lw a0, 0(a0)
+; RV64I-NEXT:    #NO_APP
+; RV64I-NEXT:    ret
   %1 = tail call i32 asm "lw $0, $1", "=r,*m"(i32* %a) nounwind
   ret i32 %1
 }