commit a42cde684126a3797f3eda9c894c379e7a8c66c1
author Nirav Dave <niravd@google.com> Tue Jan 15 17:09:23 2019 +0000
committer Nirav Dave <niravd@google.com> Tue Jan 15 17:09:23 2019 +0000
tree b293d263d915bf5b612257baaef7f0a2e9881b34
parent 4e878ddc59d14fc8aafefd1a5e9a083fb7870938

[SelectionDAG] Check membership of register in class for single
register constraints. NFCI.

Now that X86's ST(7) constraints are fixed this check can be
reinstated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351207 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 1db7d78..871ab9b 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -7429,13 +7429,8 @@
 
   // Do not check for single registers.
   if (AssignedReg) {
-    Regs.push_back(AssignedReg);
-    --NumRegs;
-    if (NumRegs) {
       for (; *I != AssignedReg; ++I)
-        assert(I != RC->end() && "Didn't find reg!");
-      ++I;
-    }
+        assert(I != RC->end() && "AssignedReg should be member of RC");
   }
 
   for (; NumRegs; --NumRegs, ++I) {