Added MIPS changes to release notes for 3.5.2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_35@232369 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/docs/ReleaseNotes.rst b/docs/ReleaseNotes.rst
index 87f96a6..d95c772 100644
--- a/docs/ReleaseNotes.rst
+++ b/docs/ReleaseNotes.rst
@@ -27,6 +27,28 @@
Changes to the MIPS Target
--------------------------
+* Corrected inline assembly to use the same assembler options as GCC for the
+ duration of the inline assembly block. Particularly, ``.set reorder``,
+ ``.set nomacro``, and ``.set noat`` are now correct.
+
+* Added ability to specify $gp as a named register global variable.
+
+* Added support for ``.set push`` and ``.set pop``.
+
+* Fixed a code generation bug in the comparison operators for MIPS32r6/MIPS64r6
+ where the compiler would use ``<`` when it should have used ``<=``.
+
+* Fixed various assertions when using 128-bit integers on 64-bit targets.
+
+* Fixed invalid use of an odd-numbered single-precision floating point register
+ when using ``-mno-odd-spreg`` with ``-msa``.
+
+Non-comprehensive list of changes in 3.5.1
+==========================================
+
+Changes to the MIPS Target
+--------------------------
+
* A large number of bugs have been fixed for big-endian Mips targets using the
N32 and N64 ABI's. Please note that some of these bugs will still affect
LLVM-IR generated by LLVM 3.5 since correct code generation depends on
