blob: 9dd3b9de260220f5485f94b17853006459c09c80 [file] [log] [blame]
..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
============================
Syntax of GFX9 Instructions
============================
.. contents::
:local:
Notation
========
Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
Introduction
============
An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document<amdgpu_syn_instructions>`.
Instructions
============
DS
-----------------------
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
ds_add_f32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_add_rtn_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_add_rtn_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_add_rtn_u64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_add_src2_f32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_add_src2_u32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_add_src2_u64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_add_u32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_add_u64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_and_b32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_and_b64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_and_rtn_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_and_rtn_b64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_and_src2_b32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_and_src2_b64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_append :ref:`vdst<amdgpu_synid9_vdst32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_bpermute_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>`
ds_cmpst_b32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata32_0>`, :ref:`vdata1<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_cmpst_b64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata64_0>`, :ref:`vdata1<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_cmpst_f32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata32_0>`, :ref:`vdata1<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_cmpst_f64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata64_0>`, :ref:`vdata1<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_cmpst_rtn_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata32_0>`, :ref:`vdata1<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_cmpst_rtn_b64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata64_0>`, :ref:`vdata1<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_cmpst_rtn_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata32_0>`, :ref:`vdata1<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_cmpst_rtn_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata64_0>`, :ref:`vdata1<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_condxchg32_rtn_b64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_consume :ref:`vdst<amdgpu_synid9_vdst32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_dec_rtn_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_dec_rtn_u64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_dec_src2_u32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_dec_src2_u64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_dec_u32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_dec_u64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_gws_barrier :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_gws_init :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_gws_sema_br :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_gws_sema_p :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_gws_sema_release_all :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_gws_sema_v :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_inc_rtn_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_inc_rtn_u64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_inc_src2_u32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_inc_src2_u64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_inc_u32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_inc_u64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_max_f32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_max_f64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_max_i32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_max_i64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_max_rtn_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_max_rtn_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_max_rtn_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_max_rtn_i64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_max_rtn_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_max_rtn_u64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_max_src2_f32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_max_src2_f64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_max_src2_i32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_max_src2_i64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_max_src2_u32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_max_src2_u64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_max_u32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_max_u64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_min_f32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_min_f64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_min_i32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_min_i64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_min_rtn_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_min_rtn_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_min_rtn_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_min_rtn_i64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_min_rtn_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_min_rtn_u64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_min_src2_f32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_min_src2_f64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_min_src2_i32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_min_src2_i64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_min_src2_u32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_min_src2_u64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_min_u32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_min_u64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_mskor_b32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata32_0>`, :ref:`vdata1<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_mskor_b64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata64_0>`, :ref:`vdata1<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_mskor_rtn_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata32_0>`, :ref:`vdata1<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_mskor_rtn_b64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata64_0>`, :ref:`vdata1<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_nop
ds_or_b32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_or_b64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_or_rtn_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_or_rtn_b64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_or_src2_b32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_or_src2_b64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_ordered_count :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_permute_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>`
ds_read2_b32 :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b32x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
ds_read2_b64 :ref:`vdst<amdgpu_synid9_vdst128_0>`::ref:`b64x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
ds_read2st64_b32 :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b32x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
ds_read2st64_b64 :ref:`vdst<amdgpu_synid9_vdst128_0>`::ref:`b64x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
ds_read_b128 :ref:`vdst<amdgpu_synid9_vdst128_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_read_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_read_b64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_read_b96 :ref:`vdst<amdgpu_synid9_vdst96_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_read_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_read_i8 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_read_i8_d16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_read_i8_d16_hi :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_read_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_read_u16_d16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_read_u16_d16_hi :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_read_u8 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_read_u8_d16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_read_u8_d16_hi :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_rsub_rtn_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_rsub_rtn_u64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_rsub_src2_u32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_rsub_src2_u64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_rsub_u32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_rsub_u64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_sub_rtn_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_sub_rtn_u64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_sub_src2_u32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_sub_src2_u64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_sub_u32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_sub_u64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_swizzle_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`pattern<amdgpu_synid_sw_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_wrap_rtn_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata32_0>`, :ref:`vdata1<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_write2_b32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata32_0>`, :ref:`vdata1<amdgpu_synid9_vdata32_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
ds_write2_b64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata64_0>`, :ref:`vdata1<amdgpu_synid9_vdata64_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
ds_write2st64_b32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata32_0>`, :ref:`vdata1<amdgpu_synid9_vdata32_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
ds_write2st64_b64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata64_0>`, :ref:`vdata1<amdgpu_synid9_vdata64_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
ds_write_b128 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata128_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_write_b16 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_write_b16_d16_hi :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_write_b32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_write_b64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_write_b8 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_write_b8_d16_hi :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_write_b96 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata96_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_write_src2_b32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_write_src2_b64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_wrxchg2_rtn_b32 :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b32x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata32_0>`, :ref:`vdata1<amdgpu_synid9_vdata32_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
ds_wrxchg2_rtn_b64 :ref:`vdst<amdgpu_synid9_vdst128_0>`::ref:`b64x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata64_0>`, :ref:`vdata1<amdgpu_synid9_vdata64_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
ds_wrxchg2st64_rtn_b32 :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b32x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata32_0>`, :ref:`vdata1<amdgpu_synid9_vdata32_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
ds_wrxchg2st64_rtn_b64 :ref:`vdst<amdgpu_synid9_vdst128_0>`::ref:`b64x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata0<amdgpu_synid9_vdata64_0>`, :ref:`vdata1<amdgpu_synid9_vdata64_0>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
ds_wrxchg_rtn_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_wrxchg_rtn_b64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_xor_b32 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_xor_b64 :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_xor_rtn_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_xor_rtn_b64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_xor_src2_b32 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
ds_xor_src2_b64 :ref:`vaddr<amdgpu_synid9_addr_ds>` :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
EXP
-----------------------
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
exp :ref:`tgt<amdgpu_synid9_tgt>`, :ref:`vsrc0<amdgpu_synid9_src_exp>`, :ref:`vsrc1<amdgpu_synid9_src_exp>`, :ref:`vsrc2<amdgpu_synid9_src_exp>`, :ref:`vsrc3<amdgpu_synid9_src_exp>` :ref:`done<amdgpu_synid_done>` :ref:`compr<amdgpu_synid_compr>` :ref:`vm<amdgpu_synid_vm>`
FLAT
-----------------------
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
flat_atomic_add :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_add_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_and :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_and_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_cmpswap :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`b32x2<amdgpu_synid9_type_dev>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata128_0>`::ref:`b64x2<amdgpu_synid9_type_dev>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_dec :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`u32<amdgpu_synid9_type_dev>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_dec_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`u64<amdgpu_synid9_type_dev>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_inc :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`u32<amdgpu_synid9_type_dev>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_inc_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`u64<amdgpu_synid9_type_dev>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_or :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_or_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_smax :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`s32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`s32<amdgpu_synid9_type_dev>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_smax_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`s64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`s64<amdgpu_synid9_type_dev>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_smin :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`s32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`s32<amdgpu_synid9_type_dev>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_smin_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`s64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`s64<amdgpu_synid9_type_dev>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_sub :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_sub_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_swap :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_swap_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_umax :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`u32<amdgpu_synid9_type_dev>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_umax_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`u64<amdgpu_synid9_type_dev>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_umin :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`u32<amdgpu_synid9_type_dev>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_umin_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`u64<amdgpu_synid9_type_dev>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_xor :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_atomic_xor_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_load_dword :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_flat>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_load_dwordx2 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_addr_flat>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_load_dwordx3 :ref:`vdst<amdgpu_synid9_vdst96_0>`, :ref:`vaddr<amdgpu_synid9_addr_flat>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_load_dwordx4 :ref:`vdst<amdgpu_synid9_vdst128_0>`, :ref:`vaddr<amdgpu_synid9_addr_flat>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_load_sbyte :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_flat>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_load_sbyte_d16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_flat>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_flat>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_load_short_d16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_flat>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_load_short_d16_hi :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_flat>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_load_sshort :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_flat>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_load_ubyte :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_flat>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_load_ubyte_d16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_flat>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_flat>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_load_ushort :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_addr_flat>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_store_byte :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_store_byte_d16_hi :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_store_dword :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_store_dwordx2 :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata64_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_store_dwordx3 :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata96_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_store_dwordx4 :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata128_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_store_short :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
flat_store_short_d16_hi :ref:`vaddr<amdgpu_synid9_addr_flat>`, :ref:`vdata<amdgpu_synid9_vdata32_0>` :ref:`offset12<amdgpu_synid_flat_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_atomic_add :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_atomic_add_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_atomic_and :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_atomic_and_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_atomic_cmpswap :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`b32x2<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_atomic_cmpswap_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata128_0>`::ref:`b64x2<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_atomic_dec :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_atomic_dec_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_atomic_inc :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_atomic_inc_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_atomic_or :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_atomic_or_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_atomic_smax :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`s32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`s32<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_atomic_smax_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`s64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`s64<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_atomic_smin :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`s32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`s32<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_atomic_smin_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`s64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`s64<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_atomic_sub :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_atomic_sub_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_atomic_swap :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_atomic_swap_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_atomic_umax :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_atomic_umax_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_atomic_umin :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_atomic_umin_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_atomic_xor :ref:`vdst<amdgpu_synid9_dst_flat_atomic32>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_atomic_xor_x2 :ref:`vdst<amdgpu_synid9_dst_flat_atomic64>`::ref:`opt<amdgpu_synid9_opt>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_load_dword :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_load_dwordx2 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_load_dwordx3 :ref:`vdst<amdgpu_synid9_vdst96_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_load_dwordx4 :ref:`vdst<amdgpu_synid9_vdst128_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_load_sbyte :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_load_sbyte_d16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_load_short_d16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_load_short_d16_hi :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_load_sshort :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_load_ubyte :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_load_ubyte_d16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_load_ushort :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_store_byte :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_store_byte_d16_hi :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_store_dword :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_store_dwordx2 :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_store_dwordx3 :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata96_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_store_dwordx4 :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata128_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_store_short :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
global_store_short_d16_hi :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_global>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
scratch_load_dword :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
scratch_load_dwordx2 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
scratch_load_dwordx3 :ref:`vdst<amdgpu_synid9_vdst96_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
scratch_load_dwordx4 :ref:`vdst<amdgpu_synid9_vdst128_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
scratch_load_sbyte :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
scratch_load_sbyte_d16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
scratch_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
scratch_load_short_d16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
scratch_load_short_d16_hi :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
scratch_load_sshort :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
scratch_load_ubyte :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
scratch_load_ubyte_d16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
scratch_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
scratch_load_ushort :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
scratch_store_byte :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
scratch_store_byte_d16_hi :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
scratch_store_dword :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
scratch_store_dwordx2 :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
scratch_store_dwordx3 :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid9_vdata96_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
scratch_store_dwordx4 :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid9_vdata128_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
scratch_store_short :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
scratch_store_short_d16_hi :ref:`vaddr<amdgpu_synid9_vaddr_flat_scratch>`, :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`saddr<amdgpu_synid9_saddr_flat_scratch>` :ref:`offset13s<amdgpu_synid_flat_offset13s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
MIMG
-----------------------
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
image_atomic_add :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
image_atomic_and :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
image_atomic_cmpswap :ref:`vdata<amdgpu_synid9_data_mimg_atomic_cmp>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
image_atomic_dec :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
image_atomic_inc :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
image_atomic_or :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
image_atomic_smax :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
image_atomic_smin :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
image_atomic_sub :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
image_atomic_swap :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
image_atomic_umax :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
image_atomic_umin :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
image_atomic_xor :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
image_gather4 :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_b :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_b_cl :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_b_cl_o :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_b_o :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_b :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_b_cl :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_b_cl_o :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_b_o :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_cl :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_cl_o :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_l :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_l_o :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_lz :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_lz_o :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_c_o :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_cl :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_cl_o :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_l :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_l_o :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_lz :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_lz_o :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_gather4_o :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_get_lod :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
image_get_resinfo :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
image_load :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_load_mip :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_load_mip_pck :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
image_load_mip_pck_sgn :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
image_load_pck :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
image_load_pck_sgn :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
image_sample :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_b :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_b_cl :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_b_cl_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_b_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_c :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_c_b :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_c_b_cl :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_c_b_cl_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_c_b_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_c_cd :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_c_cd_cl :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_c_cd_cl_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_c_cd_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_c_cl :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_c_cl_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_c_d :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_c_d_cl :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_c_d_cl_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_c_d_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_c_l :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_c_l_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_c_lz :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_c_lz_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_c_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_cd :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_cd_cl :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_cd_cl_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_cd_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_cl :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_cl_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_d :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_d_cl :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_d_cl_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_d_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_l :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_l_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_lz :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_lz_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_sample_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid9_samp_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_store :ref:`vdata<amdgpu_synid9_data_mimg_store_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_store_mip :ref:`vdata<amdgpu_synid9_data_mimg_store_d16>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
image_store_mip_pck :ref:`vdata<amdgpu_synid9_data_mimg_store>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
image_store_pck :ref:`vdata<amdgpu_synid9_data_mimg_store>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`, :ref:`srsrc<amdgpu_synid9_rsrc_mimg>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
MUBUF
-----------------------
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **SRC3** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
buffer_atomic_add :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_add_x2 :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_and :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_and_x2 :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_cmpswap :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`b32x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_cmpswap_x2 :ref:`vdata<amdgpu_synid9_data_buf_atomic128>`::ref:`dst<amdgpu_synid9_ret>`::ref:`b64x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_dec :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_dec_x2 :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_inc :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_inc_x2 :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_or :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_or_x2 :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_smax :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_smax_x2 :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_smin :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_smin_x2 :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_sub :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_sub_x2 :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_swap :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_swap_x2 :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_umax :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_umax_x2 :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_umin :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_umin_x2 :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_xor :ref:`vdata<amdgpu_synid9_data_buf_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_atomic_xor_x2 :ref:`vdata<amdgpu_synid9_data_buf_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_load_dword :ref:`vdst<amdgpu_synid9_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
buffer_load_dwordx2 :ref:`vdst<amdgpu_synid9_dst_buf_64>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_load_dwordx3 :ref:`vdst<amdgpu_synid9_dst_buf_96>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_load_dwordx4 :ref:`vdst<amdgpu_synid9_dst_buf_128>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_load_format_d16_hi_x :ref:`vdst<amdgpu_synid9_dst_buf_32>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_load_format_d16_x :ref:`vdst<amdgpu_synid9_dst_buf_32>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_load_format_d16_xy :ref:`vdst<amdgpu_synid9_dst_buf_32>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_load_format_d16_xyz :ref:`vdst<amdgpu_synid9_dst_buf_64>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_load_format_d16_xyzw :ref:`vdst<amdgpu_synid9_dst_buf_64>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_load_format_x :ref:`vdst<amdgpu_synid9_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
buffer_load_format_xy :ref:`vdst<amdgpu_synid9_dst_buf_64>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_load_format_xyz :ref:`vdst<amdgpu_synid9_dst_buf_96>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_load_format_xyzw :ref:`vdst<amdgpu_synid9_dst_buf_128>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_load_sbyte :ref:`vdst<amdgpu_synid9_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
buffer_load_sbyte_d16 :ref:`vdst<amdgpu_synid9_dst_buf_32>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_load_sbyte_d16_hi :ref:`vdst<amdgpu_synid9_dst_buf_32>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_load_short_d16 :ref:`vdst<amdgpu_synid9_dst_buf_32>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_load_short_d16_hi :ref:`vdst<amdgpu_synid9_dst_buf_32>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_load_sshort :ref:`vdst<amdgpu_synid9_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
buffer_load_ubyte :ref:`vdst<amdgpu_synid9_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
buffer_load_ubyte_d16 :ref:`vdst<amdgpu_synid9_dst_buf_32>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_load_ubyte_d16_hi :ref:`vdst<amdgpu_synid9_dst_buf_32>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_load_ushort :ref:`vdst<amdgpu_synid9_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
buffer_store_byte :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_byte_d16_hi :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_dword :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_dwordx2 :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_dwordx3 :ref:`vdata<amdgpu_synid9_vdata96_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_dwordx4 :ref:`vdata<amdgpu_synid9_vdata128_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_format_d16_hi_x :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_format_d16_x :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_format_d16_xy :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_format_d16_xyz :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_format_d16_xyzw :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_format_x :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_format_xy :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_format_xyz :ref:`vdata<amdgpu_synid9_vdata96_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_format_xyzw :ref:`vdata<amdgpu_synid9_vdata128_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_lds_dword :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`lds<amdgpu_synid_lds>`
buffer_store_short :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_store_short_d16_hi :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
buffer_wbinvl1
buffer_wbinvl1_vol
SMEM
-----------------------
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
s_atc_probe :ref:`imm3<amdgpu_synid9_perm_smem>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>`
s_atc_probe_buffer :ref:`imm3<amdgpu_synid9_perm_smem>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>`
s_atomic_add :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_atomic_add_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_atomic_and :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_atomic_and_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_atomic_cmpswap :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`b32x2<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_atomic_cmpswap_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic128>`::ref:`dst<amdgpu_synid9_ret>`::ref:`b64x2<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_atomic_dec :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_atomic_dec_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_atomic_inc :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_atomic_inc_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_atomic_or :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_atomic_or_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_atomic_smax :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s32<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_atomic_smax_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s64<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_atomic_smin :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s32<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_atomic_smin_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s64<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_atomic_sub :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_atomic_sub_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_atomic_swap :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_atomic_swap_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_atomic_umax :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_atomic_umax_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_atomic_umin :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_atomic_umin_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_atomic_xor :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_atomic_xor_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_atomic_add :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_atomic_add_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_atomic_and :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_atomic_and_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_atomic_cmpswap :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`b32x2<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_atomic_cmpswap_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic128>`::ref:`dst<amdgpu_synid9_ret>`::ref:`b64x2<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_atomic_dec :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_atomic_dec_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_atomic_inc :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_atomic_inc_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_atomic_or :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_atomic_or_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_atomic_smax :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s32<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_atomic_smax_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s64<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_atomic_smin :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s32<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_atomic_smin_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`s64<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_atomic_sub :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_atomic_sub_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_atomic_swap :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_atomic_swap_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_atomic_umax :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_atomic_umax_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_atomic_umin :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_atomic_umin_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`::ref:`u64<amdgpu_synid9_type_dev>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_atomic_xor :ref:`sdata<amdgpu_synid9_data_smem_atomic32>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_atomic_xor_x2 :ref:`sdata<amdgpu_synid9_data_smem_atomic64>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_load_dword :ref:`sdst<amdgpu_synid9_sdst32_0>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_load_dwordx16 :ref:`sdst<amdgpu_synid9_sdst512_0>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_load_dwordx2 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_load_dwordx4 :ref:`sdst<amdgpu_synid9_sdst128_0>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_load_dwordx8 :ref:`sdst<amdgpu_synid9_sdst256_0>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_store_dword :ref:`sdata<amdgpu_synid9_sdata32_0>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_store_dwordx2 :ref:`sdata<amdgpu_synid9_sdata64_0>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_buffer_store_dwordx4 :ref:`sdata<amdgpu_synid9_sdata128_0>`, :ref:`sbase<amdgpu_synid9_base_smem_buf>`, :ref:`soffset<amdgpu_synid9_offset_smem_buf>` :ref:`glc<amdgpu_synid_glc>`
s_dcache_discard :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>`
s_dcache_discard_x2 :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>`
s_dcache_inv
s_dcache_inv_vol
s_dcache_wb
s_dcache_wb_vol
s_load_dword :ref:`sdst<amdgpu_synid9_sdst32_0>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_load_dwordx16 :ref:`sdst<amdgpu_synid9_sdst512_0>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_load_dwordx2 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_load_dwordx4 :ref:`sdst<amdgpu_synid9_sdst128_0>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_load_dwordx8 :ref:`sdst<amdgpu_synid9_sdst256_0>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_memrealtime :ref:`sdst<amdgpu_synid9_sdst64_0>`
s_memtime :ref:`sdst<amdgpu_synid9_sdst64_0>`
s_scratch_load_dword :ref:`sdst<amdgpu_synid9_sdst32_0>`, :ref:`sbase<amdgpu_synid9_base_smem_scratch>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_scratch_load_dwordx2 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`sbase<amdgpu_synid9_base_smem_scratch>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_scratch_load_dwordx4 :ref:`sdst<amdgpu_synid9_sdst128_0>`, :ref:`sbase<amdgpu_synid9_base_smem_scratch>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_scratch_store_dword :ref:`sdata<amdgpu_synid9_sdata32_0>`, :ref:`sbase<amdgpu_synid9_base_smem_scratch>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_scratch_store_dwordx2 :ref:`sdata<amdgpu_synid9_sdata64_0>`, :ref:`sbase<amdgpu_synid9_base_smem_scratch>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_scratch_store_dwordx4 :ref:`sdata<amdgpu_synid9_sdata128_0>`, :ref:`sbase<amdgpu_synid9_base_smem_scratch>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_store_dword :ref:`sdata<amdgpu_synid9_sdata32_0>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_store_dwordx2 :ref:`sdata<amdgpu_synid9_sdata64_0>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
s_store_dwordx4 :ref:`sdata<amdgpu_synid9_sdata128_0>`, :ref:`sbase<amdgpu_synid9_base_smem_addr>`, :ref:`soffset<amdgpu_synid9_offset_smem_plain>` :ref:`glc<amdgpu_synid_glc>`
SOP1
-----------------------
.. parsed-literal::
**INSTRUCTION** **DST** **SRC**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
s_abs_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
s_and_saveexec_b64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
s_andn1_saveexec_b64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
s_andn1_wrexec_b64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
s_andn2_saveexec_b64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
s_andn2_wrexec_b64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
s_bcnt0_i32_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
s_bcnt0_i32_b64 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
s_bcnt1_i32_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
s_bcnt1_i32_b64 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
s_bitreplicate_b64_b32 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
s_bitset0_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
s_bitset0_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`::ref:`b32<amdgpu_synid9_type_dev>`
s_bitset1_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
s_bitset1_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`::ref:`b32<amdgpu_synid9_type_dev>`
s_brev_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
s_brev_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
s_cbranch_join :ref:`ssrc<amdgpu_synid9_ssrc32_1>`
s_cmov_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
s_cmov_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
s_ff0_i32_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
s_ff0_i32_b64 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
s_ff1_i32_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
s_ff1_i32_b64 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
s_flbit_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
s_flbit_i32_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
s_flbit_i32_b64 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
s_flbit_i32_i64 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
s_getpc_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`
s_mov_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
s_mov_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
s_mov_fed_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
s_movreld_b32 :ref:`sdst<amdgpu_synid9_sdst32_0>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
s_movreld_b64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
s_movrels_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_1>`
s_movrels_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc<amdgpu_synid9_ssrc64_1>`
s_nand_saveexec_b64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
s_nor_saveexec_b64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
s_not_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
s_not_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
s_or_saveexec_b64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
s_orn1_saveexec_b64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
s_orn2_saveexec_b64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
s_quadmask_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
s_quadmask_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
s_rfe_b64 :ref:`ssrc<amdgpu_synid9_ssrc64_1>`
s_set_gpr_idx_idx :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
s_setpc_b64 :ref:`ssrc<amdgpu_synid9_ssrc64_1>`
s_sext_i32_i16 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
s_sext_i32_i8 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
s_swappc_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc<amdgpu_synid9_ssrc64_1>`
s_wqm_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
s_wqm_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
s_xnor_saveexec_b64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
s_xor_saveexec_b64 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
SOP2
-----------------------
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
s_absdiff_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_add_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_add_u32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_addc_u32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_and_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_and_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
s_andn2_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_andn2_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
s_ashr_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
s_ashr_i64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
s_bfe_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
s_bfe_i64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
s_bfe_u32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_bfe_u64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
s_bfm_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_bfm_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`b32<amdgpu_synid9_type_dev>`
s_cbranch_g_fork :ref:`ssrc0<amdgpu_synid9_ssrc64_2>`, :ref:`ssrc1<amdgpu_synid9_ssrc64_2>`
s_cselect_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_cselect_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
s_lshl1_add_u32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_lshl2_add_u32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_lshl3_add_u32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_lshl4_add_u32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_lshl_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
s_lshl_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
s_lshr_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
s_lshr_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
s_max_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_max_u32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_min_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_min_u32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_mul_hi_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_mul_hi_u32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_mul_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_nand_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_nand_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
s_nor_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_nor_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
s_or_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_or_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
s_orn2_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_orn2_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
s_pack_hh_b32_b16 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`::ref:`b16x2<amdgpu_synid9_type_dev>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`b16x2<amdgpu_synid9_type_dev>`
s_pack_lh_b32_b16 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`b16x2<amdgpu_synid9_type_dev>`
s_pack_ll_b32_b16 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_rfe_restore_b64 :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`b32<amdgpu_synid9_type_dev>`
s_sub_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_sub_u32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_subb_u32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_xnor_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_xnor_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
s_xor_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_xor_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
SOPC
-----------------------
.. parsed-literal::
**INSTRUCTION** **SRC0** **SRC1**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
s_bitcmp0_b32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_bitcmp0_b64 :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
s_bitcmp1_b32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_bitcmp1_b64 :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`
s_cmp_eq_i32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_cmp_eq_u32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_cmp_eq_u64 :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
s_cmp_ge_i32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_cmp_ge_u32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_cmp_gt_i32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_cmp_gt_u32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_cmp_le_i32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_cmp_le_u32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_cmp_lg_i32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_cmp_lg_u32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_cmp_lg_u64 :ref:`ssrc0<amdgpu_synid9_ssrc64_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc64_0>`
s_cmp_lt_i32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_cmp_lt_u32 :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
s_set_gpr_idx_on :ref:`ssrc<amdgpu_synid9_ssrc32_0>`, :ref:`imm4<amdgpu_synid9_imm4>`
s_setvskip :ref:`ssrc0<amdgpu_synid9_ssrc32_0>`, :ref:`ssrc1<amdgpu_synid9_ssrc32_0>`
SOPK
-----------------------
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
s_addk_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`imm16<amdgpu_synid9_simm16>`
s_call_b64 :ref:`sdst<amdgpu_synid9_sdst64_1>`, :ref:`label<amdgpu_synid9_label>`
s_cbranch_i_fork :ref:`ssrc<amdgpu_synid9_ssrc64_3>`, :ref:`label<amdgpu_synid9_label>`
s_cmovk_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`imm16<amdgpu_synid9_simm16>`
s_cmpk_eq_i32 :ref:`ssrc<amdgpu_synid9_ssrc32_2>`, :ref:`imm16<amdgpu_synid9_simm16>`
s_cmpk_eq_u32 :ref:`ssrc<amdgpu_synid9_ssrc32_2>`, :ref:`imm16<amdgpu_synid9_uimm16>`
s_cmpk_ge_i32 :ref:`ssrc<amdgpu_synid9_ssrc32_2>`, :ref:`imm16<amdgpu_synid9_simm16>`
s_cmpk_ge_u32 :ref:`ssrc<amdgpu_synid9_ssrc32_2>`, :ref:`imm16<amdgpu_synid9_uimm16>`
s_cmpk_gt_i32 :ref:`ssrc<amdgpu_synid9_ssrc32_2>`, :ref:`imm16<amdgpu_synid9_simm16>`
s_cmpk_gt_u32 :ref:`ssrc<amdgpu_synid9_ssrc32_2>`, :ref:`imm16<amdgpu_synid9_uimm16>`
s_cmpk_le_i32 :ref:`ssrc<amdgpu_synid9_ssrc32_2>`, :ref:`imm16<amdgpu_synid9_simm16>`
s_cmpk_le_u32 :ref:`ssrc<amdgpu_synid9_ssrc32_2>`, :ref:`imm16<amdgpu_synid9_uimm16>`
s_cmpk_lg_i32 :ref:`ssrc<amdgpu_synid9_ssrc32_2>`, :ref:`imm16<amdgpu_synid9_simm16>`
s_cmpk_lg_u32 :ref:`ssrc<amdgpu_synid9_ssrc32_2>`, :ref:`imm16<amdgpu_synid9_uimm16>`
s_cmpk_lt_i32 :ref:`ssrc<amdgpu_synid9_ssrc32_2>`, :ref:`imm16<amdgpu_synid9_simm16>`
s_cmpk_lt_u32 :ref:`ssrc<amdgpu_synid9_ssrc32_2>`, :ref:`imm16<amdgpu_synid9_uimm16>`
s_getreg_b32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`hwreg<amdgpu_synid9_hwreg>`
s_movk_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`imm16<amdgpu_synid9_simm16>`
s_mulk_i32 :ref:`sdst<amdgpu_synid9_sdst32_1>`, :ref:`imm16<amdgpu_synid9_simm16>`
s_setreg_b32 :ref:`hwreg<amdgpu_synid9_hwreg>`, :ref:`ssrc<amdgpu_synid9_ssrc32_2>`
s_setreg_imm32_b32 :ref:`hwreg<amdgpu_synid9_hwreg>`, :ref:`imm32<amdgpu_synid9_bimm32>`
SOPP
-----------------------
.. parsed-literal::
**INSTRUCTION** **SRC**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
s_barrier
s_branch :ref:`label<amdgpu_synid9_label>`
s_cbranch_cdbgsys :ref:`label<amdgpu_synid9_label>`
s_cbranch_cdbgsys_and_user :ref:`label<amdgpu_synid9_label>`
s_cbranch_cdbgsys_or_user :ref:`label<amdgpu_synid9_label>`
s_cbranch_cdbguser :ref:`label<amdgpu_synid9_label>`
s_cbranch_execnz :ref:`label<amdgpu_synid9_label>`
s_cbranch_execz :ref:`label<amdgpu_synid9_label>`
s_cbranch_scc0 :ref:`label<amdgpu_synid9_label>`
s_cbranch_scc1 :ref:`label<amdgpu_synid9_label>`
s_cbranch_vccnz :ref:`label<amdgpu_synid9_label>`
s_cbranch_vccz :ref:`label<amdgpu_synid9_label>`
s_decperflevel :ref:`imm16<amdgpu_synid9_bimm16>`
s_endpgm
s_endpgm_ordered_ps_done
s_endpgm_saved
s_icache_inv
s_incperflevel :ref:`imm16<amdgpu_synid9_bimm16>`
s_nop :ref:`imm16<amdgpu_synid9_bimm16>`
s_sendmsg :ref:`msg<amdgpu_synid9_msg>`
s_sendmsghalt :ref:`msg<amdgpu_synid9_msg>`
s_set_gpr_idx_mode :ref:`imm4<amdgpu_synid9_imm4>`
s_set_gpr_idx_off
s_sethalt :ref:`imm16<amdgpu_synid9_bimm16>`
s_setkill :ref:`imm16<amdgpu_synid9_bimm16>`
s_setprio :ref:`imm16<amdgpu_synid9_bimm16>`
s_sleep :ref:`imm16<amdgpu_synid9_bimm16>`
s_trap :ref:`imm16<amdgpu_synid9_bimm16>`
s_ttracedata
s_waitcnt :ref:`waitcnt<amdgpu_synid9_waitcnt>`
s_wakeup
VINTRP
-----------------------
.. parsed-literal::
**INSTRUCTION** **DST** **SRC0** **SRC1**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
v_interp_mov_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`param<amdgpu_synid9_param>`::ref:`b32<amdgpu_synid9_type_dev>`, :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`
v_interp_p1_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`, :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`
v_interp_p2_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`, :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`
VOP1
-----------------------
.. parsed-literal::
**INSTRUCTION** **DST** **SRC** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
v_bfrev_b32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
v_bfrev_b32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_bfrev_b32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_ceil_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
v_ceil_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_ceil_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_ceil_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
v_ceil_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_ceil_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_ceil_f64 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src64_0>`
v_clrexcp
v_cos_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
v_cos_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_cos_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_cos_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
v_cos_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_cos_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_cvt_f16_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
v_cvt_f16_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_cvt_f16_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_cvt_f16_i16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
v_cvt_f16_i16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_cvt_f16_i16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_cvt_f16_u16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
v_cvt_f16_u16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_cvt_f16_u16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_cvt_f32_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
v_cvt_f32_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_cvt_f32_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_cvt_f32_f64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src64_0>`
v_cvt_f32_i32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
v_cvt_f32_i32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_cvt_f32_i32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_cvt_f32_u32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
v_cvt_f32_u32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_cvt_f32_u32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_cvt_f32_ubyte0 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
v_cvt_f32_ubyte0_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_cvt_f32_ubyte0_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_cvt_f32_ubyte1 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
v_cvt_f32_ubyte1_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_cvt_f32_ubyte1_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_cvt_f32_ubyte2 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
v_cvt_f32_ubyte2_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_cvt_f32_ubyte2_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_cvt_f32_ubyte3 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
v_cvt_f32_ubyte3_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_cvt_f32_ubyte3_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_cvt_f64_f32 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src32_0>`
v_cvt_f64_i32 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src32_0>`
v_cvt_f64_u32 :ref:`vdst<amdgpu_synid9_vdst64_0>`, :ref:`src<amdgpu_synid9_src32_0>`
v_cvt_flr_i32_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
v_cvt_flr_i32_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_cvt_flr_i32_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_cvt_i16_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
v_cvt_i16_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_cvt_i16_f16_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_cvt_i32_f32 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
v_cvt_i32_f32_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
v_cvt_i32_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
v_cvt_i32_f64 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src64_0>`
v_cvt_norm_i16_f16 :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`src<amdgpu_synid9_src32_0>`
v_cvt_norm_i16_f16_dpp :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :r