test/CodeGen/AArch64/GlobalISel/select-stlxr-intrin.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

--- |
  define i32 @test_store_release_i64(i32 %a, i64* %addr) {
    ret i32 %a
  }
...
---
name:            test_store_release_i64
alignment:       2
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $w0, $x1, $x2

    ; CHECK-LABEL: name: test_store_release_i64
    ; CHECK: liveins: $w0, $x1, $x2
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
    ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
    ; CHECK: early-clobber %2:gpr32 = STLXRX [[COPY]], [[COPY1]]
    ; CHECK: $w0 = COPY %2
    ; CHECK: RET_ReallyLR implicit $w0
    %1:gpr(s64) = COPY $x1
    %2:gpr(p0) = COPY $x2
    %3:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stlxr), %1(s64), %2(p0) :: (volatile store 8 into %ir.addr)
    $w0 = COPY %3(s32)
    RET_ReallyLR implicit $w0

...