[X86] Turn (and (shl X, C1), C2) into (shl (and X, (C1 >> C2), C2) if the AND could match a movzx.
Could get further improvements by recognizing (i64 and (anyext (i32 shl))).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358737 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 67ba3c5..c98cea8 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -4009,6 +4009,9 @@
ShiftedVal = (uint64_t)Val >> ShAmt;
if (NVT == MVT::i64 && !isUInt<32>(Val) && isUInt<32>(ShiftedVal))
return true;
+ // Also swap order when the AND can become MOVZX.
+ if (ShiftedVal == UINT8_MAX || ShiftedVal == UINT16_MAX)
+ return true;
}
ShiftedVal = Val >> ShAmt;
if ((!isInt<8>(Val) && isInt<8>(ShiftedVal)) ||
diff --git a/test/CodeGen/X86/narrow-shl-cst.ll b/test/CodeGen/X86/narrow-shl-cst.ll
index 0100a8c..86fc7a1 100644
--- a/test/CodeGen/X86/narrow-shl-cst.ll
+++ b/test/CodeGen/X86/narrow-shl-cst.ll
@@ -201,9 +201,8 @@
define i32 @test17(i32 %x) nounwind {
; CHECK-LABEL: test17:
; CHECK: # %bb.0:
-; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: movzbl %dil, %eax
; CHECK-NEXT: shll $10, %eax
-; CHECK-NEXT: andl $261120, %eax # imm = 0x3FC00
; CHECK-NEXT: retq
%and = shl i32 %x, 10
%shl = and i32 %and, 261120
@@ -225,9 +224,8 @@
define i32 @test19(i32 %x) nounwind {
; CHECK-LABEL: test19:
; CHECK: # %bb.0:
-; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: movzwl %di, %eax
; CHECK-NEXT: shll $10, %eax
-; CHECK-NEXT: andl $67107840, %eax # imm = 0x3FFFC00
; CHECK-NEXT: retq
%and = shl i32 %x, 10
%shl = and i32 %and, 67107840
