| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s |
| |
| --- |
| |
| name: shrink_scalar_imm_vgpr_v_add_i32_e64_no_carry_out_use |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_no_carry_out_use |
| ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345 |
| ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF |
| ; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec |
| ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]] |
| %0:sreg_32_xm0 = S_MOV_B32 12345 |
| %1:vgpr_32 = IMPLICIT_DEF |
| %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec |
| S_ENDPGM 0, implicit %2 |
| |
| ... |
| |
| --- |
| |
| name: shrink_vgpr_scalar_imm_v_add_i32_e64_no_carry_out_use |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| ; GCN-LABEL: name: shrink_vgpr_scalar_imm_v_add_i32_e64_no_carry_out_use |
| ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF |
| ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345 |
| ; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec |
| ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]] |
| %0:vgpr_32 = IMPLICIT_DEF |
| %1:sreg_32_xm0 = S_MOV_B32 12345 |
| %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec |
| S_ENDPGM 0, implicit %2 |
| |
| ... |
| --- |
| |
| name: shrink_scalar_imm_vgpr_v_add_i32_e64_carry_out_use |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_carry_out_use |
| ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345 |
| ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF |
| ; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec |
| ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]] |
| %0:sreg_32_xm0 = S_MOV_B32 12345 |
| %1:vgpr_32 = IMPLICIT_DEF |
| %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec |
| S_ENDPGM 0, implicit %2 |
| |
| ... |
| --- |
| |
| # This does not shrink because it would violate the constant bus |
| # restriction. to have an SGPR input and an immediate, so a copy would |
| # be required. |
| |
| name: shrink_vector_imm_sgpr_v_add_i32_e64_no_carry_out_use |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| ; GCN-LABEL: name: shrink_vector_imm_sgpr_v_add_i32_e64_no_carry_out_use |
| ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec |
| ; GCN: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF |
| ; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[DEF]], [[V_MOV_B32_e32_]], 0, implicit $exec |
| ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]] |
| %0:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec |
| %1:sreg_32_xm0 = IMPLICIT_DEF |
| %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec |
| S_ENDPGM 0, implicit %2 |
| |
| ... |
| |
| --- |
| |
| name: shrink_sgpr_vector_imm_v_add_i32_e64_no_carry_out_use |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| ; GCN-LABEL: name: shrink_sgpr_vector_imm_v_add_i32_e64_no_carry_out_use |
| ; GCN: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF |
| ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec |
| ; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[V_MOV_B32_e32_]], [[DEF]], 0, implicit $exec |
| ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]] |
| %0:sreg_32_xm0 = IMPLICIT_DEF |
| %1:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec |
| %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec |
| S_ENDPGM 0, implicit %2 |
| |
| ... |
| |
| --- |
| |
| name: shrink_scalar_imm_vgpr_v_add_i32_e64_live_vcc_use |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_live_vcc_use |
| ; GCN: $vcc = S_MOV_B64 -1 |
| ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345 |
| ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF |
| ; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[S_MOV_B32_]], [[DEF]], 0, implicit $exec |
| ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit $vcc |
| $vcc = S_MOV_B64 -1 |
| %0:sreg_32_xm0 = S_MOV_B32 12345 |
| %1:vgpr_32 = IMPLICIT_DEF |
| %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec |
| S_ENDPGM 0, implicit %2, implicit $vcc |
| |
| ... |
| |
| --- |
| |
| name: shrink_scalar_imm_vgpr_v_add_i32_e64_liveout_vcc_use |
| tracksRegLiveness: true |
| |
| body: | |
| ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_liveout_vcc_use |
| ; GCN: bb.0: |
| ; GCN: successors: %bb.1(0x80000000) |
| ; GCN: $vcc = S_MOV_B64 -1 |
| ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345 |
| ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF |
| ; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[S_MOV_B32_]], [[DEF]], 0, implicit $exec |
| ; GCN: bb.1: |
| ; GCN: liveins: $vcc |
| ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit $vcc |
| bb.0: |
| successors: %bb.1 |
| $vcc = S_MOV_B64 -1 |
| %0:sreg_32_xm0 = S_MOV_B32 12345 |
| %1:vgpr_32 = IMPLICIT_DEF |
| %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec |
| |
| bb.1: |
| liveins: $vcc |
| S_ENDPGM 0, implicit %2, implicit $vcc |
| |
| ... |
| --- |
| |
| name: shrink_scalar_imm_vgpr_v_add_i32_e64_liveout_vcc_lo_use |
| tracksRegLiveness: true |
| |
| body: | |
| ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_liveout_vcc_lo_use |
| ; GCN: bb.0: |
| ; GCN: successors: %bb.1(0x80000000) |
| ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345 |
| ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF |
| ; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[S_MOV_B32_]], [[DEF]], 0, implicit $exec |
| ; GCN: bb.1: |
| ; GCN: liveins: $vcc_lo |
| ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit $vcc_lo |
| bb.0: |
| successors: %bb.1 |
| $vcc = S_MOV_B64 -1 |
| %0:sreg_32_xm0 = S_MOV_B32 12345 |
| %1:vgpr_32 = IMPLICIT_DEF |
| %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec |
| |
| bb.1: |
| liveins: $vcc_lo |
| S_ENDPGM 0, implicit %2, implicit $vcc_lo |
| |
| ... |
| --- |
| |
| # This is not OK to clobber because vcc_lo has a livein use. |
| |
| name: shrink_scalar_imm_vgpr_v_add_i32_e64_livein_vcc |
| tracksRegLiveness: true |
| |
| body: | |
| ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_livein_vcc |
| ; GCN: bb.0: |
| ; GCN: successors: %bb.1(0x80000000) |
| ; GCN: $vcc = S_MOV_B64 -1 |
| ; GCN: bb.1: |
| ; GCN: liveins: $vcc |
| ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345 |
| ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF |
| ; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[S_MOV_B32_]], [[DEF]], 0, implicit $exec |
| ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit $vcc_lo |
| bb.0: |
| successors: %bb.1 |
| $vcc = S_MOV_B64 -1 |
| |
| bb.1: |
| liveins: $vcc |
| %0:sreg_32_xm0 = S_MOV_B32 12345 |
| %1:vgpr_32 = IMPLICIT_DEF |
| %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec |
| S_ENDPGM 0, implicit %2, implicit $vcc_lo |
| |
| ... |
| --- |
| |
| name: shrink_scalar_imm_vgpr_v_add_i32_e64_livein_vcc_hi |
| tracksRegLiveness: true |
| |
| body: | |
| ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_livein_vcc_hi |
| ; GCN: bb.0: |
| ; GCN: successors: %bb.1(0x80000000) |
| ; GCN: $vcc_hi = S_MOV_B32 -1 |
| ; GCN: bb.1: |
| ; GCN: successors: %bb.2(0x80000000) |
| ; GCN: liveins: $vcc_hi |
| ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345 |
| ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF |
| ; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[S_MOV_B32_]], [[DEF]], 0, implicit $exec |
| ; GCN: bb.2: |
| ; GCN: liveins: $vcc_hi |
| ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e64_]], implicit $vcc_hi |
| bb.0: |
| successors: %bb.1 |
| $vcc_hi = S_MOV_B32 -1 |
| |
| bb.1: |
| liveins: $vcc_hi |
| %0:sreg_32_xm0 = S_MOV_B32 12345 |
| %1:vgpr_32 = IMPLICIT_DEF |
| %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec |
| |
| bb.2: |
| liveins: $vcc_hi |
| |
| S_ENDPGM 0, implicit %2, implicit $vcc_hi |
| |
| ... |
| |
| --- |
| |
| name: shrink_scalar_imm_vgpr_v_sub_i32_e64_no_carry_out_use |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_sub_i32_e64_no_carry_out_use |
| ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345 |
| ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF |
| ; GCN: [[V_SUBREV_I32_e32_:%[0-9]+]]:vgpr_32 = V_SUBREV_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec |
| ; GCN: S_ENDPGM 0, implicit [[V_SUBREV_I32_e32_]] |
| %0:sreg_32_xm0 = S_MOV_B32 12345 |
| %1:vgpr_32 = IMPLICIT_DEF |
| %2:vgpr_32, %3:sreg_64 = V_SUB_I32_e64 %0, %1, 0, implicit $exec |
| S_ENDPGM 0, implicit %2 |
| |
| ... |
| |
| --- |
| |
| name: shrink_vgpr_scalar_imm_v_sub_i32_e64_no_carry_out_use |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| ; GCN-LABEL: name: shrink_vgpr_scalar_imm_v_sub_i32_e64_no_carry_out_use |
| ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF |
| ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345 |
| ; GCN: [[V_SUB_I32_e32_:%[0-9]+]]:vgpr_32 = V_SUB_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec |
| ; GCN: S_ENDPGM 0, implicit [[V_SUB_I32_e32_]] |
| %0:vgpr_32 = IMPLICIT_DEF |
| %1:sreg_32_xm0 = S_MOV_B32 12345 |
| %2:vgpr_32, %3:sreg_64 = V_SUB_I32_e64 %0, %1, 0, implicit $exec |
| S_ENDPGM 0, implicit %2 |
| |
| ... |
| |
| --- |
| |
| name: shrink_scalar_imm_vgpr_v_subrev_i32_e64_no_carry_out_use |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_subrev_i32_e64_no_carry_out_use |
| ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345 |
| ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF |
| ; GCN: [[V_SUB_I32_e32_:%[0-9]+]]:vgpr_32 = V_SUB_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec |
| ; GCN: S_ENDPGM 0, implicit [[V_SUB_I32_e32_]] |
| %0:sreg_32_xm0 = S_MOV_B32 12345 |
| %1:vgpr_32 = IMPLICIT_DEF |
| %2:vgpr_32, %3:sreg_64 = V_SUBREV_I32_e64 %0, %1, 0, implicit $exec |
| S_ENDPGM 0, implicit %2 |
| |
| ... |
| |
| --- |
| |
| name: shrink_vgpr_scalar_imm_v_subrev_i32_e64_no_carry_out_use |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| ; GCN-LABEL: name: shrink_vgpr_scalar_imm_v_subrev_i32_e64_no_carry_out_use |
| ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF |
| ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345 |
| ; GCN: [[V_SUBREV_I32_e32_:%[0-9]+]]:vgpr_32 = V_SUBREV_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec |
| ; GCN: S_ENDPGM 0, implicit [[V_SUBREV_I32_e32_]] |
| %0:vgpr_32 = IMPLICIT_DEF |
| %1:sreg_32_xm0 = S_MOV_B32 12345 |
| %2:vgpr_32, %3:sreg_64 = V_SUBREV_I32_e64 %0, %1, 0, implicit $exec |
| S_ENDPGM 0, implicit %2 |
| |
| ... |
| |
| --- |
| |
| # We know this is OK because vcc isn't live out of the block. |
| |
| name: shrink_scalar_imm_vgpr_v_add_i32_e64_known_no_liveout |
| tracksRegLiveness: true |
| |
| body: | |
| ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_known_no_liveout |
| ; GCN: bb.0: |
| ; GCN: successors: %bb.1(0x80000000) |
| ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345 |
| ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF |
| ; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec |
| ; GCN: bb.1: |
| ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]] |
| bb.0: |
| successors: %bb.1 |
| |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| %0:sreg_32_xm0 = S_MOV_B32 12345 |
| %1:vgpr_32 = IMPLICIT_DEF |
| %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec |
| S_NOP 0 |
| S_NOP 0 |
| |
| bb.1: |
| S_ENDPGM 0, implicit %2 |
| |
| ... |
| |
| --- |
| |
| # We know this is OK because vcc isn't live out of the block, even |
| # though it had a defined but unused. value |
| |
| name: shrink_scalar_imm_vgpr_v_add_i32_e64_known_no_liveout_dead_vcc_def |
| tracksRegLiveness: true |
| |
| body: | |
| ; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_known_no_liveout_dead_vcc_def |
| ; GCN: bb.0: |
| ; GCN: successors: %bb.1(0x80000000) |
| ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345 |
| ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF |
| ; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec |
| ; GCN: bb.1: |
| ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]] |
| bb.0: |
| successors: %bb.1 |
| |
| S_NOP 0, implicit-def $vcc |
| %0:sreg_32_xm0 = S_MOV_B32 12345 |
| %1:vgpr_32 = IMPLICIT_DEF |
| %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec |
| S_NOP 0 |
| S_NOP 0 |
| |
| bb.1: |
| S_ENDPGM 0, implicit %2 |
| |
| ... |
| --- |
| |
| # This requires searching through many DBG_VALUE instructions before the insert poitn, which |
| # should not count against the search limit. |
| |
| name: vcc_liveness_dbg_value_search_before |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| ; GCN-LABEL: name: vcc_liveness_dbg_value_search_before |
| ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345 |
| ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec |
| ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]] |
| %0:sreg_32_xm0 = S_MOV_B32 12345 |
| %1:vgpr_32 = IMPLICIT_DEF |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec |
| S_ENDPGM 0, implicit %2 |
| |
| ... |
| --- |
| |
| # This requires searching through many DBG_VALUE instructions after the insert point, which |
| # should not count against the search limit. |
| |
| name: vcc_liveness_dbg_value_search_after |
| tracksRegLiveness: true |
| |
| body: | |
| bb.0: |
| ; GCN-LABEL: name: vcc_liveness_dbg_value_search_after |
| ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345 |
| ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF |
| ; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: DBG_VALUE $noreg, 0 |
| ; GCN: S_ENDPGM 0, implicit [[V_ADD_I32_e32_]] |
| %0:sreg_32_xm0 = S_MOV_B32 12345 |
| %1:vgpr_32 = IMPLICIT_DEF |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| S_NOP 0 |
| %2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, 0, implicit $exec |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| DBG_VALUE $noreg, 0 |
| $vcc = S_MOV_B64 0 |
| S_ENDPGM 0, implicit %2 |
| |
| ... |