test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s

---
name: insert_vector_elt_0_v2s32

body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-LABEL: name: insert_vector_elt_0_v2s32
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
    ; CHECK: [[INSERT:%[0-9]+]]:_(<2 x s32>) = G_INSERT [[COPY]], [[COPY1]](s32), 0
    ; CHECK: $vgpr0_vgpr1 = COPY [[INSERT]](<2 x s32>)
    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
    %1:_(s32) = COPY $vgpr2
    %2:_(s32) = G_CONSTANT i32 0
    %3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
    $vgpr0_vgpr1 = COPY %3
...

---
name: insert_vector_elt_1_v2s32

body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-LABEL: name: insert_vector_elt_1_v2s32
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
    ; CHECK: [[INSERT:%[0-9]+]]:_(<2 x s32>) = G_INSERT [[COPY]], [[COPY1]](s32), 32
    ; CHECK: $vgpr0_vgpr1 = COPY [[INSERT]](<2 x s32>)
    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
    %1:_(s32) = COPY $vgpr2
    %2:_(s32) = G_CONSTANT i32 1
    %3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
    $vgpr0_vgpr1 = COPY %3
...

---
name: insert_vector_elt_2_v2s32

body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-LABEL: name: insert_vector_elt_2_v2s32
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
    ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
    ; CHECK: $vgpr0_vgpr1 = COPY [[DEF]](<2 x s32>)
    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
    %1:_(s32) = COPY $vgpr2
    %2:_(s32) = G_CONSTANT i32 2
    %3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
    $vgpr0_vgpr1 = COPY %3
...

---
name: insert_vector_elt_v2s32_varidx_i64

body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3_vgpr4

    ; CHECK-LABEL: name: insert_vector_elt_v2s32_varidx_i64
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
    ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $vgpr3_vgpr4
    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
    ; CHECK: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[TRUNC]](s32)
    ; CHECK: $vgpr0_vgpr1 = COPY [[IVEC]](<2 x s32>)
    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
    %1:_(s32) = COPY $vgpr2
    %2:_(s64) = COPY $vgpr3_vgpr4
    %3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
    $vgpr0_vgpr1 = COPY %3
...

---
name: insert_vector_elt_v16s32_varidx_i64

body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16, $vgpr17_vgpr18

    ; CHECK-LABEL: name: insert_vector_elt_v16s32_varidx_i64
    ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr16
    ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $vgpr17_vgpr18
    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
    ; CHECK: [[IVEC:%[0-9]+]]:_(<16 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[TRUNC]](s32)
    ; CHECK: S_ENDPGM 0, implicit [[IVEC]](<16 x s32>)
    %0:_(<16 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
    %1:_(s32) = COPY $vgpr16
    %2:_(s64) = COPY $vgpr17_vgpr18
    %3:_(<16 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
    S_ENDPGM 0, implicit %3
...

---
name: insert_vector_elt_0_v16s64

body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: insert_vector_elt_0_v16s64
    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
    ; CHECK: [[DEF:%[0-9]+]]:_(<16 x s64>) = G_IMPLICIT_DEF
    ; CHECK: [[INSERT:%[0-9]+]]:_(<16 x s64>) = G_INSERT [[DEF]], [[COPY]](s64), 0
    ; CHECK: S_ENDPGM 0, implicit [[INSERT]](<16 x s64>)
    %0:_(s64) = COPY $vgpr0_vgpr1
    %1:_(<16 x s64>) = G_IMPLICIT_DEF
    %2:_(s32) = G_CONSTANT i32 0
    %3:_(<16 x s64>) = G_INSERT_VECTOR_ELT %1, %0, %2
    S_ENDPGM 0, implicit %3
...