test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=WAVE64 %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=WAVE32 %s

---
name: legal_brcond_vcc
body:             |
  ; WAVE64-LABEL: name: legal_brcond_vcc
  ; WAVE64: bb.0:
  ; WAVE64:   successors: %bb.1(0x80000000)
  ; WAVE64:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; WAVE64:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; WAVE64:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
  ; WAVE64:   G_BRCOND [[ICMP]](s1), %bb.1
  ; WAVE64: bb.1:
  ; WAVE32-LABEL: name: legal_brcond_vcc
  ; WAVE32: bb.0:
  ; WAVE32:   successors: %bb.1(0x80000000)
  ; WAVE32:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; WAVE32:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; WAVE32:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
  ; WAVE32:   G_BRCOND [[ICMP]](s1), %bb.1
  ; WAVE32: bb.1:
  bb.0:
    successors: %bb.1
    liveins: $vgpr0, $vgpr1
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s1) = G_ICMP intpred(ne), %0, %1
    G_BRCOND %2, %bb.1

  bb.1:
...

---

name: legal_brcond_scc

body: |
  ; WAVE64-LABEL: name: legal_brcond_scc
  ; WAVE64: bb.0:
  ; WAVE64:   successors: %bb.1(0x80000000)
  ; WAVE64:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
  ; WAVE64:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
  ; WAVE64:   [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
  ; WAVE64:   G_BRCOND [[ICMP]](s1), %bb.1
  ; WAVE64: bb.1:
  ; WAVE32-LABEL: name: legal_brcond_scc
  ; WAVE32: bb.0:
  ; WAVE32:   successors: %bb.1(0x80000000)
  ; WAVE32:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
  ; WAVE32:   [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
  ; WAVE32:   [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
  ; WAVE32:   G_BRCOND [[ICMP]](s1), %bb.1
  ; WAVE32: bb.1:
  bb.0:
    liveins: $sgpr0, $sgpr1

    %0:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = COPY $sgpr1
    %2:scc(s1) = G_ICMP intpred(eq), %0, %1
    G_BRCOND %2, %bb.1

  bb.1:

...

---
name: brcond_si_if
body:             |
  ; WAVE64-LABEL: name: brcond_si_if
  ; WAVE64: bb.0:
  ; WAVE64:   successors: %bb.1(0x80000000)
  ; WAVE64:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; WAVE64:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; WAVE64:   [[ICMP:%[0-9]+]]:sreg_64_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
  ; WAVE64:   [[SI_IF:%[0-9]+]]:sreg_64_xexec(s64) = SI_IF [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
  ; WAVE64: bb.1:
  ; WAVE32-LABEL: name: brcond_si_if
  ; WAVE32: bb.0:
  ; WAVE32:   successors: %bb.1(0x80000000)
  ; WAVE32:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; WAVE32:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; WAVE32:   [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
  ; WAVE32:   [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_IF [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
  ; WAVE32: bb.1:
  bb.0:
    successors: %bb.1
    liveins: $vgpr0, $vgpr1
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s1) = G_ICMP intpred(ne), %0, %1
    %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2
    G_BRCOND %3, %bb.1

  bb.1:
...

---
name: brcond_si_loop
body:             |
  ; WAVE64-LABEL: name: brcond_si_loop
  ; WAVE64: bb.0:
  ; WAVE64:   successors: %bb.1(0x80000000)
  ; WAVE64:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; WAVE64:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; WAVE64:   [[COPY2:%[0-9]+]]:sreg_64_xexec(s64) = COPY $sgpr0_sgpr1
  ; WAVE64:   SI_LOOP [[COPY2]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
  ; WAVE64: bb.1:
  ; WAVE32-LABEL: name: brcond_si_loop
  ; WAVE32: bb.0:
  ; WAVE32:   successors: %bb.1(0x80000000)
  ; WAVE32:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
  ; WAVE32:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
  ; WAVE32:   [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY $sgpr0_sgpr1
  ; WAVE32:   SI_LOOP [[COPY2]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
  ; WAVE32: bb.1:
  bb.0:
    successors: %bb.1
    liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s64) = COPY $sgpr0_sgpr1
    %3:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), %2
    G_BRCOND %3, %bb.1

  bb.1:
...