test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefix=GCN

---

name:            fptoui
legalized:       true
regBankSelected: true

body: |
  bb.0:
    liveins: $sgpr0, $vgpr0, $vgpr3_vgpr4

    ; GCN-LABEL: name: fptoui
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
    ; GCN: [[V_CVT_U32_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_CVT_U32_F32_e64_1:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e64 0, [[COPY1]], 0, 0, implicit $exec
    ; GCN: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_U32_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GCN: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_U32_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = COPY $vgpr0

    %2:vgpr(p1) = COPY $vgpr3_vgpr4

    ; fptoui s
    %3:vgpr(s32) = G_FPTOUI %0

    ; fptoui v
    %4:vgpr(s32) = G_FPTOUI %1

    G_STORE %3, %2 :: (store 4, addrspace 1)
    G_STORE %4, %2 :: (store 4, addrspace 1)
...

---
name: fptoui_s16_to_s32_vv
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $vgpr0

    ; GCN-LABEL: name: fptoui_s16_to_s32_vv
    ; GCN: liveins: $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[COPY]], implicit $exec
    ; GCN: [[V_CVT_U32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $exec
    ; GCN: $vgpr0 = COPY [[V_CVT_U32_F32_e32_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s32) = G_FPTOUI %1
    $vgpr0 = COPY %2
...

---
name: fptoui_s16_to_s32_vs
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0

    ; GCN-LABEL: name: fptoui_s16_to_s32_vs
    ; GCN: liveins: $sgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[COPY]], implicit $exec
    ; GCN: [[V_CVT_U32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $exec
    ; GCN: $vgpr0 = COPY [[V_CVT_U32_F32_e32_]]
    %0:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s16) = G_TRUNC %0
    %2:vgpr(s32) = G_FPTOUI %1
    $vgpr0 = COPY %2
...

---
name: fptoui_s16_to_s32_fneg_vv
legalized: true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $vgpr0

    ; GCN-LABEL: name: fptoui_s16_to_s32_fneg_vv
    ; GCN: liveins: $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
    ; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
    ; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[V_XOR_B32_e32_]], implicit $exec
    ; GCN: [[V_CVT_U32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $exec
    ; GCN: $vgpr0 = COPY [[V_CVT_U32_F32_e32_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_FNEG %1
    %3:vgpr(s32) = G_FPTOUI %2
    $vgpr0 = COPY %3
...