| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select -mattr=-fullfp16 -global-isel %s -o - | FileCheck %s |
| |
| ... |
| --- |
| name: test_f16.rint |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| machineFunctionInfo: {} |
| body: | |
| bb.0: |
| liveins: $h0 |
| |
| ; CHECK-LABEL: name: test_f16.rint |
| ; CHECK: liveins: $h0 |
| ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0 |
| ; CHECK: [[FCVTSHr:%[0-9]+]]:fpr32 = FCVTSHr [[COPY]] |
| ; CHECK: [[FRINTXSr:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr]] |
| ; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr]] |
| ; CHECK: $h0 = COPY [[FCVTHSr]] |
| ; CHECK: RET_ReallyLR implicit $h0 |
| %0:fpr(s16) = COPY $h0 |
| %2:fpr(s32) = G_FPEXT %0(s16) |
| %3:fpr(s32) = G_FRINT %2 |
| %1:fpr(s16) = G_FPTRUNC %3(s32) |
| $h0 = COPY %1(s16) |
| RET_ReallyLR implicit $h0 |
| |
| ... |
| --- |
| name: test_v4f16.rint |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| machineFunctionInfo: {} |
| body: | |
| bb.0: |
| liveins: $d0 |
| |
| ; CHECK-LABEL: name: test_v4f16.rint |
| ; CHECK: liveins: $d0 |
| ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 |
| ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub |
| ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub |
| ; CHECK: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[COPY]], %subreg.dsub |
| ; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY [[INSERT_SUBREG]].hsub |
| ; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG]], 1 |
| ; CHECK: [[CPYi16_1:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG1]], 2 |
| ; CHECK: [[CPYi16_2:%[0-9]+]]:fpr16 = CPYi16 [[INSERT_SUBREG2]], 3 |
| ; CHECK: [[FCVTSHr:%[0-9]+]]:fpr32 = FCVTSHr [[COPY1]] |
| ; CHECK: [[FRINTXSr:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr]] |
| ; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr]] |
| ; CHECK: [[FCVTSHr1:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_]] |
| ; CHECK: [[FRINTXSr1:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr1]] |
| ; CHECK: [[FCVTHSr1:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr1]] |
| ; CHECK: [[FCVTSHr2:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_1]] |
| ; CHECK: [[FRINTXSr2:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr2]] |
| ; CHECK: [[FCVTHSr2:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr2]] |
| ; CHECK: [[FCVTSHr3:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_2]] |
| ; CHECK: [[FRINTXSr3:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr3]] |
| ; CHECK: [[FCVTHSr3:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr3]] |
| ; CHECK: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[FCVTHSr]], %subreg.hsub |
| ; CHECK: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[FCVTHSr1]], %subreg.hsub |
| ; CHECK: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG3]], 1, [[INSERT_SUBREG4]], 0 |
| ; CHECK: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], [[FCVTHSr2]], %subreg.hsub |
| ; CHECK: [[INSvi16lane1:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane]], 2, [[INSERT_SUBREG5]], 0 |
| ; CHECK: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], [[FCVTHSr3]], %subreg.hsub |
| ; CHECK: [[INSvi16lane2:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane1]], 3, [[INSERT_SUBREG6]], 0 |
| ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi16lane2]].dsub |
| ; CHECK: $d0 = COPY [[COPY2]] |
| ; CHECK: RET_ReallyLR implicit $d0 |
| %0:fpr(<4 x s16>) = COPY $d0 |
| %2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16) = G_UNMERGE_VALUES %0(<4 x s16>) |
| %16:fpr(s32) = G_FPEXT %2(s16) |
| %17:fpr(s32) = G_FRINT %16 |
| %6:fpr(s16) = G_FPTRUNC %17(s32) |
| %14:fpr(s32) = G_FPEXT %3(s16) |
| %15:fpr(s32) = G_FRINT %14 |
| %7:fpr(s16) = G_FPTRUNC %15(s32) |
| %12:fpr(s32) = G_FPEXT %4(s16) |
| %13:fpr(s32) = G_FRINT %12 |
| %8:fpr(s16) = G_FPTRUNC %13(s32) |
| %10:fpr(s32) = G_FPEXT %5(s16) |
| %11:fpr(s32) = G_FRINT %10 |
| %9:fpr(s16) = G_FPTRUNC %11(s32) |
| %1:fpr(<4 x s16>) = G_BUILD_VECTOR %6(s16), %7(s16), %8(s16), %9(s16) |
| $d0 = COPY %1(<4 x s16>) |
| RET_ReallyLR implicit $d0 |
| |
| ... |
| --- |
| name: test_v8f16.rint |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| machineFunctionInfo: {} |
| body: | |
| bb.0: |
| liveins: $q0 |
| |
| ; CHECK-LABEL: name: test_v8f16.rint |
| ; CHECK: liveins: $q0 |
| ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 |
| ; CHECK: [[COPY1:%[0-9]+]]:fpr16 = COPY [[COPY]].hsub |
| ; CHECK: [[CPYi16_:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 1 |
| ; CHECK: [[CPYi16_1:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 2 |
| ; CHECK: [[CPYi16_2:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 3 |
| ; CHECK: [[CPYi16_3:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 4 |
| ; CHECK: [[CPYi16_4:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 5 |
| ; CHECK: [[CPYi16_5:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 6 |
| ; CHECK: [[CPYi16_6:%[0-9]+]]:fpr16 = CPYi16 [[COPY]], 7 |
| ; CHECK: [[FCVTSHr:%[0-9]+]]:fpr32 = FCVTSHr [[COPY1]] |
| ; CHECK: [[FRINTXSr:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr]] |
| ; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr]] |
| ; CHECK: [[FCVTSHr1:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_]] |
| ; CHECK: [[FRINTXSr1:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr1]] |
| ; CHECK: [[FCVTHSr1:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr1]] |
| ; CHECK: [[FCVTSHr2:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_1]] |
| ; CHECK: [[FRINTXSr2:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr2]] |
| ; CHECK: [[FCVTHSr2:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr2]] |
| ; CHECK: [[FCVTSHr3:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_2]] |
| ; CHECK: [[FRINTXSr3:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr3]] |
| ; CHECK: [[FCVTHSr3:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr3]] |
| ; CHECK: [[FCVTSHr4:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_3]] |
| ; CHECK: [[FRINTXSr4:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr4]] |
| ; CHECK: [[FCVTHSr4:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr4]] |
| ; CHECK: [[FCVTSHr5:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_4]] |
| ; CHECK: [[FRINTXSr5:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr5]] |
| ; CHECK: [[FCVTHSr5:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr5]] |
| ; CHECK: [[FCVTSHr6:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_5]] |
| ; CHECK: [[FRINTXSr6:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr6]] |
| ; CHECK: [[FCVTHSr6:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr6]] |
| ; CHECK: [[FCVTSHr7:%[0-9]+]]:fpr32 = FCVTSHr [[CPYi16_6]] |
| ; CHECK: [[FRINTXSr7:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr7]] |
| ; CHECK: [[FCVTHSr7:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr7]] |
| ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[FCVTHSr]], %subreg.hsub |
| ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[FCVTHSr1]], %subreg.hsub |
| ; CHECK: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0 |
| ; CHECK: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[FCVTHSr2]], %subreg.hsub |
| ; CHECK: [[INSvi16lane1:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane]], 2, [[INSERT_SUBREG2]], 0 |
| ; CHECK: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[FCVTHSr3]], %subreg.hsub |
| ; CHECK: [[INSvi16lane2:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane1]], 3, [[INSERT_SUBREG3]], 0 |
| ; CHECK: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[FCVTHSr4]], %subreg.hsub |
| ; CHECK: [[INSvi16lane3:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane2]], 4, [[INSERT_SUBREG4]], 0 |
| ; CHECK: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], [[FCVTHSr5]], %subreg.hsub |
| ; CHECK: [[INSvi16lane4:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane3]], 5, [[INSERT_SUBREG5]], 0 |
| ; CHECK: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], [[FCVTHSr6]], %subreg.hsub |
| ; CHECK: [[INSvi16lane5:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane4]], 6, [[INSERT_SUBREG6]], 0 |
| ; CHECK: [[DEF7:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG7:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF7]], [[FCVTHSr7]], %subreg.hsub |
| ; CHECK: [[INSvi16lane6:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane5]], 7, [[INSERT_SUBREG7]], 0 |
| ; CHECK: $q0 = COPY [[INSvi16lane6]] |
| ; CHECK: RET_ReallyLR implicit $q0 |
| %0:fpr(<8 x s16>) = COPY $q0 |
| %2:fpr(s16), %3:fpr(s16), %4:fpr(s16), %5:fpr(s16), %6:fpr(s16), %7:fpr(s16), %8:fpr(s16), %9:fpr(s16) = G_UNMERGE_VALUES %0(<8 x s16>) |
| %32:fpr(s32) = G_FPEXT %2(s16) |
| %33:fpr(s32) = G_FRINT %32 |
| %10:fpr(s16) = G_FPTRUNC %33(s32) |
| %30:fpr(s32) = G_FPEXT %3(s16) |
| %31:fpr(s32) = G_FRINT %30 |
| %11:fpr(s16) = G_FPTRUNC %31(s32) |
| %28:fpr(s32) = G_FPEXT %4(s16) |
| %29:fpr(s32) = G_FRINT %28 |
| %12:fpr(s16) = G_FPTRUNC %29(s32) |
| %26:fpr(s32) = G_FPEXT %5(s16) |
| %27:fpr(s32) = G_FRINT %26 |
| %13:fpr(s16) = G_FPTRUNC %27(s32) |
| %24:fpr(s32) = G_FPEXT %6(s16) |
| %25:fpr(s32) = G_FRINT %24 |
| %14:fpr(s16) = G_FPTRUNC %25(s32) |
| %22:fpr(s32) = G_FPEXT %7(s16) |
| %23:fpr(s32) = G_FRINT %22 |
| %15:fpr(s16) = G_FPTRUNC %23(s32) |
| %20:fpr(s32) = G_FPEXT %8(s16) |
| %21:fpr(s32) = G_FRINT %20 |
| %16:fpr(s16) = G_FPTRUNC %21(s32) |
| %18:fpr(s32) = G_FPEXT %9(s16) |
| %19:fpr(s32) = G_FRINT %18 |
| %17:fpr(s16) = G_FPTRUNC %19(s32) |
| %1:fpr(<8 x s16>) = G_BUILD_VECTOR %10(s16), %11(s16), %12(s16), %13(s16), %14(s16), %15(s16), %16(s16), %17(s16) |
| $q0 = COPY %1(<8 x s16>) |
| RET_ReallyLR implicit $q0 |
