test/CodeGen/AArch64/GlobalISel/select-arith-shifted-reg.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

---
name:            add_shl_s64_rhs
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0
    ; CHECK-LABEL: name: add_shl_s64_rhs
    ; CHECK: liveins: $x0
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
    ; CHECK: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY]], [[COPY]], 8
    ; CHECK: $x0 = COPY [[ADDXrs]]
    ; CHECK: RET_ReallyLR implicit $x0
    %0:gpr(s64) = COPY $x0
    %1:gpr(s64) = G_CONSTANT i64 8
    %2:gpr(s64) = G_SHL %0, %1:gpr(s64)
    %3:gpr(s64) = G_ADD %0, %2:gpr(s64)
    $x0 = COPY %3:gpr(s64)
    RET_ReallyLR implicit $x0

...
---
name:            add_shl_s64_lhs
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0, $x1
    ; CHECK-LABEL: name: add_shl_s64_lhs
    ; CHECK: liveins: $x0, $x1
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
    ; CHECK: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY1]], [[COPY]], 8
    ; CHECK: $x0 = COPY [[ADDXrs]]
    ; CHECK: RET_ReallyLR implicit $x0
    %0:gpr(s64) = COPY $x0
    %4:gpr(s64) = COPY $x1
    %1:gpr(s64) = G_CONSTANT i64 8
    %2:gpr(s64) = G_SHL %0, %1:gpr(s64)
    %3:gpr(s64) = G_ADD %2, %4:gpr(s64)
    $x0 = COPY %3:gpr(s64)
    RET_ReallyLR implicit $x0

...
---
name:            sub_shl_s64_rhs
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0
    ; CHECK-LABEL: name: sub_shl_s64_rhs
    ; CHECK: liveins: $x0
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
    ; CHECK: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs [[COPY]], [[COPY]], 8, implicit-def $nzcv
    ; CHECK: $x0 = COPY [[SUBSXrs]]
    ; CHECK: RET_ReallyLR implicit $x0
    %0:gpr(s64) = COPY $x0
    %1:gpr(s64) = G_CONSTANT i64 8
    %2:gpr(s64) = G_SHL %0, %1:gpr(s64)
    %3:gpr(s64) = G_SUB %0, %2:gpr(s64)
    $x0 = COPY %3:gpr(s64)
    RET_ReallyLR implicit $x0

---
name:            add_lshr_s64_rhs
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0
    %0:gpr(s64) = COPY $x0
    %1:gpr(s64) = G_CONSTANT i64 8
    %2:gpr(s64) = G_LSHR %0, %1:gpr(s64)
    %3:gpr(s64) = G_ADD %0, %2:gpr(s64)
    $x0 = COPY %3:gpr(s64)
    RET_ReallyLR implicit $x0

...
---
name:            add_lshr_s64_lhs
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0, $x1
    ; CHECK-LABEL: name: add_lshr_s64_lhs
    ; CHECK: liveins: $x0, $x1
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
    ; CHECK: %param2:gpr64 = COPY $x1
    ; CHECK: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs %param2, [[COPY]], 72
    ; CHECK: $x0 = COPY [[ADDXrs]]
    ; CHECK: RET_ReallyLR implicit $x0
    %0:gpr(s64) = COPY $x0
    %param2:gpr(s64) = COPY $x1
    %1:gpr(s64) = G_CONSTANT i64 8
    %2:gpr(s64) = G_LSHR %0, %1:gpr(s64)
    %3:gpr(s64) = G_ADD %2, %param2:gpr(s64)
    $x0 = COPY %3:gpr(s64)
    RET_ReallyLR implicit $x0

...
---
name:            sub_lshr_s64_rhs
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0
    ; CHECK-LABEL: name: sub_lshr_s64_rhs
    ; CHECK: liveins: $x0
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
    ; CHECK: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs [[COPY]], [[COPY]], 72, implicit-def $nzcv
    ; CHECK: $x0 = COPY [[SUBSXrs]]
    ; CHECK: RET_ReallyLR implicit $x0
    %0:gpr(s64) = COPY $x0
    %1:gpr(s64) = G_CONSTANT i64 8
    %2:gpr(s64) = G_LSHR %0, %1:gpr(s64)
    %3:gpr(s64) = G_SUB %0, %2:gpr(s64)
    $x0 = COPY %3:gpr(s64)
    RET_ReallyLR implicit $x0

...
---
name:            add_ashr_s64_rhs
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0
    ; CHECK-LABEL: name: add_ashr_s64_rhs
    ; CHECK: liveins: $x0
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
    ; CHECK: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY]], [[COPY]], 136
    ; CHECK: $x0 = COPY [[ADDXrs]]
    ; CHECK: RET_ReallyLR implicit $x0
    %0:gpr(s64) = COPY $x0
    %1:gpr(s64) = G_CONSTANT i64 8
    %2:gpr(s64) = G_ASHR %0, %1:gpr(s64)
    %3:gpr(s64) = G_ADD %0, %2:gpr(s64)
    $x0 = COPY %3:gpr(s64)
    RET_ReallyLR implicit $x0

...
---
name:            add_ashr_s64_lhs
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0, $x1
    ; CHECK-LABEL: name: add_ashr_s64_lhs
    ; CHECK: liveins: $x0, $x1
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
    ; CHECK: %param2:gpr64 = COPY $x1
    ; CHECK: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs %param2, [[COPY]], 136
    ; CHECK: $x0 = COPY [[ADDXrs]]
    ; CHECK: RET_ReallyLR implicit $x0
    %0:gpr(s64) = COPY $x0
    %param2:gpr(s64) = COPY $x1
    %1:gpr(s64) = G_CONSTANT i64 8
    %2:gpr(s64) = G_ASHR %0, %1:gpr(s64)
    %3:gpr(s64) = G_ADD %2, %param2:gpr(s64)
    $x0 = COPY %3:gpr(s64)
    RET_ReallyLR implicit $x0

...
---
name:            sub_ashr_s64_rhs
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0
    ; CHECK-LABEL: name: sub_ashr_s64_rhs
    ; CHECK: liveins: $x0
    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
    ; CHECK: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs [[COPY]], [[COPY]], 136, implicit-def $nzcv
    ; CHECK: $x0 = COPY [[SUBSXrs]]
    ; CHECK: RET_ReallyLR implicit $x0
    %0:gpr(s64) = COPY $x0
    %1:gpr(s64) = G_CONSTANT i64 8
    %2:gpr(s64) = G_ASHR %0, %1:gpr(s64)
    %3:gpr(s64) = G_SUB %0, %2:gpr(s64)
    $x0 = COPY %3:gpr(s64)
    RET_ReallyLR implicit $x0

---
name:            add_shl_s32_rhs
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $w0
    %0:gpr(s32) = COPY $w0
    %1:gpr(s32) = G_CONSTANT i32 8
    %2:gpr(s32) = G_SHL %0, %1:gpr(s32)
    %3:gpr(s32) = G_ADD %0, %2:gpr(s32)
    $w0 = COPY %3:gpr(s32)
    RET_ReallyLR implicit $w0

...
---
name:            add_shl_s32_lhs
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $w0, $w1
    ; CHECK-LABEL: name: add_shl_s32_lhs
    ; CHECK: liveins: $w0, $w1
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK: %param2:gpr32 = COPY $w1
    ; CHECK: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs %param2, [[COPY]], 8
    ; CHECK: $w0 = COPY [[ADDWrs]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:gpr(s32) = COPY $w0
    %param2:gpr(s32) = COPY $w1
    %1:gpr(s32) = G_CONSTANT i32 8
    %2:gpr(s32) = G_SHL %0, %1:gpr(s32)
    %3:gpr(s32) = G_ADD %2, %param2:gpr(s32)
    $w0 = COPY %3:gpr(s32)
    RET_ReallyLR implicit $w0

...
---
name:            sub_shl_s32_rhs
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $w0
    ; CHECK-LABEL: name: sub_shl_s32_rhs
    ; CHECK: liveins: $w0
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs [[COPY]], [[COPY]], 8, implicit-def $nzcv
    ; CHECK: $w0 = COPY [[SUBSWrs]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:gpr(s32) = COPY $w0
    %1:gpr(s32) = G_CONSTANT i32 8
    %2:gpr(s32) = G_SHL %0, %1:gpr(s32)
    %3:gpr(s32) = G_SUB %0, %2:gpr(s32)
    $w0 = COPY %3:gpr(s32)
    RET_ReallyLR implicit $w0

...
---
name:            add_lshr_s32_rhs
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $w0
    ; CHECK-LABEL: name: add_lshr_s32_rhs
    ; CHECK: liveins: $w0
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs [[COPY]], [[COPY]], 72
    ; CHECK: $w0 = COPY [[ADDWrs]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:gpr(s32) = COPY $w0
    %1:gpr(s32) = G_CONSTANT i32 8
    %2:gpr(s32) = G_LSHR %0, %1:gpr(s32)
    %3:gpr(s32) = G_ADD %0, %2:gpr(s32)
    $w0 = COPY %3:gpr(s32)
    RET_ReallyLR implicit $w0

...
---
name:            add_lshr_s32_lhs
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $w0, $w1
    ; CHECK-LABEL: name: add_lshr_s32_lhs
    ; CHECK: liveins: $w0, $w1
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK: %param2:gpr32 = COPY $w1
    ; CHECK: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs %param2, [[COPY]], 72
    ; CHECK: $w0 = COPY [[ADDWrs]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:gpr(s32) = COPY $w0
    %param2:gpr(s32) = COPY $w1
    %1:gpr(s32) = G_CONSTANT i32 8
    %2:gpr(s32) = G_LSHR %0, %1:gpr(s32)
    %3:gpr(s32) = G_ADD %2, %param2:gpr(s32)
    $w0 = COPY %3:gpr(s32)
    RET_ReallyLR implicit $w0

...
---
name:            sub_lshr_s32_rhs
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $w0
    ; CHECK-LABEL: name: sub_lshr_s32_rhs
    ; CHECK: liveins: $w0
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs [[COPY]], [[COPY]], 72, implicit-def $nzcv
    ; CHECK: $w0 = COPY [[SUBSWrs]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:gpr(s32) = COPY $w0
    %1:gpr(s32) = G_CONSTANT i32 8
    %2:gpr(s32) = G_LSHR %0, %1:gpr(s32)
    %3:gpr(s32) = G_SUB %0, %2:gpr(s32)
    $w0 = COPY %3:gpr(s32)
    RET_ReallyLR implicit $w0

...
---
name:            add_ashr_s32_rhs
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $w0
    ; CHECK-LABEL: name: add_ashr_s32_rhs
    ; CHECK: liveins: $w0
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs [[COPY]], [[COPY]], 136
    ; CHECK: $w0 = COPY [[ADDWrs]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:gpr(s32) = COPY $w0
    %1:gpr(s32) = G_CONSTANT i32 8
    %2:gpr(s32) = G_ASHR %0, %1:gpr(s32)
    %3:gpr(s32) = G_ADD %0, %2:gpr(s32)
    $w0 = COPY %3:gpr(s32)
    RET_ReallyLR implicit $w0

...
---
name:            add_ashr_s32_lhs
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $w0, $w1
    ; CHECK-LABEL: name: add_ashr_s32_lhs
    ; CHECK: liveins: $w0, $w1
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK: %param2:gpr32 = COPY $w1
    ; CHECK: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs %param2, [[COPY]], 136
    ; CHECK: $w0 = COPY [[ADDWrs]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:gpr(s32) = COPY $w0
    %param2:gpr(s32) = COPY $w1
    %1:gpr(s32) = G_CONSTANT i32 8
    %2:gpr(s32) = G_ASHR %0, %1:gpr(s32)
    %3:gpr(s32) = G_ADD %2, %param2:gpr(s32)
    $w0 = COPY %3:gpr(s32)
    RET_ReallyLR implicit $w0

...
---
name:            sub_ashr_s32_rhs
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $w0
    ; CHECK-LABEL: name: sub_ashr_s32_rhs
    ; CHECK: liveins: $w0
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs [[COPY]], [[COPY]], 136, implicit-def $nzcv
    ; CHECK: $w0 = COPY [[SUBSWrs]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:gpr(s32) = COPY $w0
    %1:gpr(s32) = G_CONSTANT i32 8
    %2:gpr(s32) = G_ASHR %0, %1:gpr(s32)
    %3:gpr(s32) = G_SUB %0, %2:gpr(s32)
    $w0 = COPY %3:gpr(s32)
    RET_ReallyLR implicit $w0