commit 82647e1dc565f3ef6f07ec296e534358500f15fe
author Evandro Menezes <e.menezes@samsung.com> Fri Jan 11 22:39:47 2019 +0000
committer Evandro Menezes <e.menezes@samsung.com> Fri Jan 11 22:39:47 2019 +0000
tree 0d747083e4aa2f176b9fb4a775c6da8e646df877
parent 83f886b8d1577117e6f7dd6fd11041609436b3cb

[AArch64] Improve Exynos predicates

Expand the predicate using shifted arithmetic and logic instructions to also
consider the respective not shifted instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350976 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/AArch64/AArch64SchedPredExynos.td

diff --git a/lib/Target/AArch64/AArch64SchedPredExynos.td b/lib/Target/AArch64/AArch64SchedPredExynos.td
index 2044e30..48c5423 100644
--- a/lib/Target/AArch64/AArch64SchedPredExynos.td
+++ b/lib/Target/AArch64/AArch64SchedPredExynos.td
@@ -48,7 +48,10 @@
                                                CheckExtBy3]>]>]>>>,
                            MCOpcodeSwitchCase<
                              IsArithShiftOp.ValidOpcodes,
-                             MCReturnStatement<ExynosCheckShift>>],
+                             MCReturnStatement<ExynosCheckShift>>,
+                           MCOpcodeSwitchCase<
+                             IsArithUnshiftOp.ValidOpcodes,
+                             MCReturnStatement<TruePred>>],
                           MCReturnStatement<FalsePred>>>;
 def ExynosArithPred : MCSchedPredicate<ExynosArithFn>;
 
@@ -58,7 +61,10 @@
                         MCOpcodeSwitchStatement<
                           [MCOpcodeSwitchCase<
                              IsLogicShiftOp.ValidOpcodes,
-                             MCReturnStatement<ExynosCheckShift>>],
+                             MCReturnStatement<ExynosCheckShift>>,
+                           MCOpcodeSwitchCase<
+                             IsLogicUnshiftOp.ValidOpcodes,
+                             MCReturnStatement<TruePred>>],
                           MCReturnStatement<FalsePred>>>;
 def ExynosLogicPred : MCSchedPredicate<ExynosLogicFn>;
 
@@ -73,7 +79,10 @@
                                    [ExynosCheckShift,
                                     CheckAll<
                                      [CheckShiftLSL,
-                                      CheckShiftBy8]>]>>>],
+                                      CheckShiftBy8]>]>>>,
+                             MCOpcodeSwitchCase<
+                               IsLogicUnshiftOp.ValidOpcodes,
+                               MCReturnStatement<TruePred>>],
                             MCReturnStatement<FalsePred>>>;
 def ExynosLogicExPred : MCSchedPredicate<ExynosLogicExFn>;