blob: eb058bc9b7d8454d6525cdc47dea7ddaab3ca72d [file] [log] [blame]
# RUN: llc -run-pass ppc-mi-peepholes -ppc-convert-rr-to-ri %s -o - -verify-machineinstrs | FileCheck %s
# RUN: llc -start-after ppc-mi-peepholes -ppc-late-peephole %s -o - -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-LATE
--- |
; ModuleID = 'convert-rr-to-ri-instrs.ll'
source_filename = "convert-rr-to-ri-instrs.c"
target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu"
; Function Attrs: norecurse nounwind readnone
define signext i32 @testADD4(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
entry:
%add = add nsw i32 %a, 33
%add1 = add nsw i32 %add, %b
ret i32 %add1
}
; Function Attrs: norecurse nounwind readnone
define i64 @testADD8(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%add = add nsw i64 %a, 33
%add1 = add nsw i64 %add, %b
ret i64 %add1
}
; Function Attrs: norecurse nounwind readnone
define i128 @testADDC(i128 %a, i128 %b) local_unnamed_addr #0 {
entry:
%add = add nsw i128 %b, %a
ret i128 %add
}
; Function Attrs: norecurse nounwind readnone
define i128 @testADDC8(i128 %a, i128 %b) local_unnamed_addr #0 {
entry:
%add = add nsw i128 %b, %a
ret i128 %add
}
; Function Attrs: norecurse nounwind readnone
define i64 @testADDCo(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%add = add nsw i64 %b, %a
%cmp = icmp eq i64 %add, 0
%neg = sext i1 %cmp to i64
%retval.0 = xor i64 %add, %neg
ret i64 %retval.0
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @testADDI(i32 signext %a) local_unnamed_addr #0 {
entry:
%add = add nsw i32 %a, 44
ret i32 %add
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @testADDI8(i32 signext %a) local_unnamed_addr #0 {
entry:
%add = add nsw i32 %a, 44
ret i32 %add
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @testANDo(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%and = and i64 %b, %a
%tobool = icmp eq i64 %and, 0
%cond = select i1 %tobool, i64 %b, i64 %a
%conv = trunc i64 %cond to i32
ret i32 %conv
}
; Function Attrs: norecurse nounwind readnone
define i64 @testAND8o(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%and = and i64 %b, %a
%tobool = icmp eq i64 %and, 0
%cond = select i1 %tobool, i64 %b, i64 %a
ret i64 %cond
}
; Function Attrs: norecurse nounwind readnone
define i64 @testCMPD(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%cmp = icmp sgt i64 %a, %b
%add = select i1 %cmp, i64 0, i64 %a
%cond = add nsw i64 %add, %b
ret i64 %cond
}
; Function Attrs: norecurse nounwind readnone
define i64 @testCMPDI(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%cmp = icmp sgt i64 %a, 87
%add = select i1 %cmp, i64 0, i64 %a
%cond = add nsw i64 %add, %b
ret i64 %cond
}
; Function Attrs: norecurse nounwind readnone
define i64 @testCMPDI_F(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%cmp = icmp sgt i64 %a, 87
%add = select i1 %cmp, i64 0, i64 %a
%cond = add nsw i64 %add, %b
ret i64 %cond
}
; Function Attrs: norecurse nounwind readnone
define i64 @testCMPLD(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%cmp = icmp ugt i64 %a, %b
%add = select i1 %cmp, i64 0, i64 %a
%cond = add i64 %add, %b
ret i64 %cond
}
; Function Attrs: norecurse nounwind readnone
define i64 @testCMPLDI(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%cmp = icmp ugt i64 %a, 87
%add = select i1 %cmp, i64 0, i64 %a
%cond = add i64 %add, %b
ret i64 %cond
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @testCMPW(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
entry:
%cmp = icmp sgt i32 %a, %b
%add = select i1 %cmp, i32 0, i32 %a
%cond = add nsw i32 %add, %b
ret i32 %cond
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @testCMPWI(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
entry:
%cmp = icmp sgt i32 %a, 87
%add = select i1 %cmp, i32 0, i32 %a
%cond = add nsw i32 %add, %b
ret i32 %cond
}
; Function Attrs: norecurse nounwind readnone
define zeroext i32 @testCMPLW(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
entry:
%cmp = icmp ugt i32 %a, %b
%add = select i1 %cmp, i32 0, i32 %a
%cond = add i32 %add, %b
ret i32 %cond
}
; Function Attrs: norecurse nounwind readnone
define zeroext i32 @testCMPLWI(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
entry:
%cmp = icmp ugt i32 %a, 87
%add = select i1 %cmp, i32 0, i32 %a
%cond = add i32 %add, %b
ret i32 %cond
}
; Function Attrs: norecurse nounwind readonly
define zeroext i8 @testLBZUX(i8* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #1 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds i8, i8* %ptr, i64 %idxprom
%0 = load i8, i8* %arrayidx, align 1, !tbaa !3
%conv = zext i8 %0 to i32
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds i8, i8* %ptr, i64 %idxprom2
%1 = load i8, i8* %arrayidx3, align 1, !tbaa !3
%conv4 = zext i8 %1 to i32
%add5 = add nuw nsw i32 %conv4, %conv
%conv6 = trunc i32 %add5 to i8
ret i8 %conv6
}
; Function Attrs: norecurse nounwind readonly
define zeroext i8 @testLBZX(i8* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #1 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds i8, i8* %ptr, i64 %idxprom
%0 = load i8, i8* %arrayidx, align 1, !tbaa !3
%conv = zext i8 %0 to i32
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds i8, i8* %ptr, i64 %idxprom2
%1 = load i8, i8* %arrayidx3, align 1, !tbaa !3
%conv4 = zext i8 %1 to i32
%add5 = add nuw nsw i32 %conv4, %conv
%conv6 = trunc i32 %add5 to i8
ret i8 %conv6
}
; Function Attrs: norecurse nounwind readonly
define zeroext i16 @testLHZUX(i16* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #1 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds i16, i16* %ptr, i64 %idxprom
%0 = load i16, i16* %arrayidx, align 2, !tbaa !6
%conv = zext i16 %0 to i32
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds i16, i16* %ptr, i64 %idxprom2
%1 = load i16, i16* %arrayidx3, align 2, !tbaa !6
%conv4 = zext i16 %1 to i32
%add5 = add nuw nsw i32 %conv4, %conv
%conv6 = trunc i32 %add5 to i16
ret i16 %conv6
}
; Function Attrs: norecurse nounwind readonly
define zeroext i16 @testLHZX(i16* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #1 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds i16, i16* %ptr, i64 %idxprom
%0 = load i16, i16* %arrayidx, align 2, !tbaa !6
%conv = zext i16 %0 to i32
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds i16, i16* %ptr, i64 %idxprom2
%1 = load i16, i16* %arrayidx3, align 2, !tbaa !6
%conv4 = zext i16 %1 to i32
%add5 = add nuw nsw i32 %conv4, %conv
%conv6 = trunc i32 %add5 to i16
ret i16 %conv6
}
; Function Attrs: norecurse nounwind readonly
define signext i16 @testLHAUX(i16* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #1 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds i16, i16* %ptr, i64 %idxprom
%0 = load i16, i16* %arrayidx, align 2, !tbaa !6
%conv9 = zext i16 %0 to i32
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds i16, i16* %ptr, i64 %idxprom2
%1 = load i16, i16* %arrayidx3, align 2, !tbaa !6
%conv410 = zext i16 %1 to i32
%add5 = add nuw nsw i32 %conv410, %conv9
%conv6 = trunc i32 %add5 to i16
ret i16 %conv6
}
; Function Attrs: norecurse nounwind readonly
define signext i16 @testLHAX(i16* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #1 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds i16, i16* %ptr, i64 %idxprom
%0 = load i16, i16* %arrayidx, align 2, !tbaa !6
%conv9 = zext i16 %0 to i32
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds i16, i16* %ptr, i64 %idxprom2
%1 = load i16, i16* %arrayidx3, align 2, !tbaa !6
%conv410 = zext i16 %1 to i32
%add5 = add nuw nsw i32 %conv410, %conv9
%conv6 = trunc i32 %add5 to i16
ret i16 %conv6
}
; Function Attrs: norecurse nounwind readonly
define zeroext i32 @testLWZUX(i32* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #1 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds i32, i32* %ptr, i64 %idxprom
%0 = load i32, i32* %arrayidx, align 4, !tbaa !8
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds i32, i32* %ptr, i64 %idxprom2
%1 = load i32, i32* %arrayidx3, align 4, !tbaa !8
%add4 = add i32 %1, %0
ret i32 %add4
}
; Function Attrs: norecurse nounwind readonly
define zeroext i32 @testLWZX(i32* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #1 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds i32, i32* %ptr, i64 %idxprom
%0 = load i32, i32* %arrayidx, align 4, !tbaa !8
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds i32, i32* %ptr, i64 %idxprom2
%1 = load i32, i32* %arrayidx3, align 4, !tbaa !8
%add4 = add i32 %1, %0
ret i32 %add4
}
; Function Attrs: norecurse nounwind readonly
define i64 @testLWAX(i32* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #1 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds i32, i32* %ptr, i64 %idxprom
%0 = load i32, i32* %arrayidx, align 4, !tbaa !8
%conv = sext i32 %0 to i64
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds i32, i32* %ptr, i64 %idxprom2
%1 = load i32, i32* %arrayidx3, align 4, !tbaa !8
%conv4 = sext i32 %1 to i64
%add5 = add nsw i64 %conv4, %conv
ret i64 %add5
}
; Function Attrs: norecurse nounwind readonly
define i64 @testLDUX(i64* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #1 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds i64, i64* %ptr, i64 %idxprom
%0 = load i64, i64* %arrayidx, align 8, !tbaa !10
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds i64, i64* %ptr, i64 %idxprom2
%1 = load i64, i64* %arrayidx3, align 8, !tbaa !10
%add4 = add i64 %1, %0
ret i64 %add4
}
; Function Attrs: norecurse nounwind readonly
define i64 @testLDX(i64* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #1 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds i64, i64* %ptr, i64 %idxprom
%0 = load i64, i64* %arrayidx, align 8, !tbaa !10
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds i64, i64* %ptr, i64 %idxprom2
%1 = load i64, i64* %arrayidx3, align 8, !tbaa !10
%add4 = add i64 %1, %0
ret i64 %add4
}
; Function Attrs: norecurse nounwind readonly
define double @testLFDUX(double* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #2 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds double, double* %ptr, i64 %idxprom
%0 = load double, double* %arrayidx, align 8, !tbaa !12
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds double, double* %ptr, i64 %idxprom2
%1 = load double, double* %arrayidx3, align 8, !tbaa !12
%add4 = fadd double %0, %1
ret double %add4
}
; Function Attrs: norecurse nounwind readonly
define double @testLFDX(double* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #2 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds double, double* %ptr, i64 %idxprom
%0 = load double, double* %arrayidx, align 8, !tbaa !12
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds double, double* %ptr, i64 %idxprom2
%1 = load double, double* %arrayidx3, align 8, !tbaa !12
%add4 = fadd double %0, %1
ret double %add4
}
; Function Attrs: norecurse nounwind readonly
define <4 x float> @testLFSUX(float* nocapture readonly %ptr, i32 signext %idx) local_unnamed_addr #2 {
entry:
%idxprom = sext i32 %idx to i64
%arrayidx = getelementptr inbounds float, float* %ptr, i64 %idxprom
%0 = load float, float* %arrayidx, align 4, !tbaa !14
%conv = fptoui float %0 to i32
%vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
%1 = bitcast float* %ptr to i8*
%2 = shl i64 %idxprom, 2
%uglygep = getelementptr i8, i8* %1, i64 %2
%uglygep2 = getelementptr i8, i8* %uglygep, i64 4
%3 = bitcast i8* %uglygep2 to float*
%4 = load float, float* %3, align 4, !tbaa !14
%conv3 = fptoui float %4 to i32
%vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
%uglygep5 = getelementptr i8, i8* %uglygep, i64 8
%5 = bitcast i8* %uglygep5 to float*
%6 = load float, float* %5, align 4, !tbaa !14
%conv8 = fptoui float %6 to i32
%vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
%uglygep8 = getelementptr i8, i8* %uglygep, i64 12
%7 = bitcast i8* %uglygep8 to float*
%8 = load float, float* %7, align 4, !tbaa !14
%conv13 = fptoui float %8 to i32
%vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
%9 = bitcast <4 x i32> %vecinit14 to <4 x float>
ret <4 x float> %9
}
; Function Attrs: norecurse nounwind readonly
define float @testLFSX(float* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #2 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds float, float* %ptr, i64 %idxprom
%0 = load float, float* %arrayidx, align 4, !tbaa !14
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds float, float* %ptr, i64 %idxprom2
%1 = load float, float* %arrayidx3, align 4, !tbaa !14
%add4 = fadd float %0, %1
ret float %add4
}
; Function Attrs: norecurse nounwind readonly
define double @testLXSDX(double* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #1 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds double, double* %ptr, i64 %idxprom
%0 = load double, double* %arrayidx, align 8, !tbaa !12
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds double, double* %ptr, i64 %idxprom2
%1 = load double, double* %arrayidx3, align 8, !tbaa !12
%add4 = fadd double %0, %1
ret double %add4
}
; Function Attrs: norecurse nounwind readonly
define float @testLXSSPX(float* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #1 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds float, float* %ptr, i64 %idxprom
%0 = load float, float* %arrayidx, align 4, !tbaa !14
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds float, float* %ptr, i64 %idxprom2
%1 = load float, float* %arrayidx3, align 4, !tbaa !14
%add4 = fadd float %0, %1
ret float %add4
}
; Function Attrs: norecurse nounwind readonly
define <4 x i32> @testLXVX(<4 x i32>* nocapture readonly %ptr, i32 zeroext %idx) local_unnamed_addr #1 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds <4 x i32>, <4 x i32>* %ptr, i64 %idxprom
%0 = load <4 x i32>, <4 x i32>* %arrayidx, align 16, !tbaa !3
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds <4 x i32>, <4 x i32>* %ptr, i64 %idxprom2
%1 = load <4 x i32>, <4 x i32>* %arrayidx3, align 16, !tbaa !3
%add4 = add <4 x i32> %1, %0
ret <4 x i32> %add4
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @testOR(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
entry:
%or = or i32 %b, %a
ret i32 %or
}
; Function Attrs: norecurse nounwind readnone
define i64 @testOR8(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%or = or i64 %b, %a
ret i64 %or
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @testORI(i32 signext %a) local_unnamed_addr #0 {
entry:
%or = or i32 %a, 88
ret i32 %or
}
; Function Attrs: norecurse nounwind readnone
define i64 @testORI8(i64 %a) local_unnamed_addr #0 {
entry:
%or = or i64 %a, 99
ret i64 %or
}
; Function Attrs: norecurse nounwind readnone
define i64 @testRLDCL(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%and = and i64 %b, 63
%shl = shl i64 %a, %and
%sub = sub nsw i64 64, %and
%shr = lshr i64 %a, %sub
%or = or i64 %shr, %shl
ret i64 %or
}
; Function Attrs: norecurse nounwind readnone
define i64 @testRLDCLo(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%and = and i64 %b, 63
%shl = shl i64 %a, %and
%sub = sub nsw i64 64, %and
%shr = lshr i64 %a, %sub
%or = or i64 %shr, %shl
%tobool = icmp eq i64 %or, 0
%cond = select i1 %tobool, i64 %and, i64 %a
ret i64 %cond
}
; Function Attrs: norecurse nounwind readnone
define i64 @testRLDCR(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%and = and i64 %b, 63
%shl = shl i64 %a, %and
%sub = sub nsw i64 64, %and
%shr = lshr i64 %a, %sub
%or = or i64 %shr, %shl
ret i64 %or
}
; Function Attrs: norecurse nounwind readnone
define i64 @testRLDCRo(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%and = and i64 %b, 63
%shl = shl i64 %a, %and
%sub = sub nsw i64 64, %and
%shr = lshr i64 %a, %sub
%or = or i64 %shr, %shl
%tobool = icmp eq i64 %or, 0
%cond = select i1 %tobool, i64 %and, i64 %a
ret i64 %cond
}
; Function Attrs: norecurse nounwind readnone
define i64 @testRLDICL(i64 %a) local_unnamed_addr #0 {
entry:
%shr = lshr i64 %a, 11
%and = and i64 %shr, 16777215
ret i64 %and
}
; Function Attrs: norecurse nounwind readnone
define i64 @testRLDICLo(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%shr = lshr i64 %a, 11
%and = and i64 %shr, 16777215
%tobool = icmp eq i64 %and, 0
%cond = select i1 %tobool, i64 %b, i64 %and
ret i64 %cond
}
; Function Attrs: norecurse nounwind readnone
define i64 @testRLDICLo2(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%shr = lshr i64 %a, 11
%and = and i64 %shr, 16777215
%tobool = icmp eq i64 %and, 0
%cond = select i1 %tobool, i64 %b, i64 %and
ret i64 %cond
}
; Function Attrs: norecurse nounwind readnone
define i64 @testRLDICLo3(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%shr = lshr i64 %a, 11
%and = and i64 %shr, 16777215
%tobool = icmp eq i64 %and, 0
%cond = select i1 %tobool, i64 %b, i64 %and
ret i64 %cond
}
; Function Attrs: norecurse nounwind readnone
define zeroext i32 @testRLWINM(i32 zeroext %a) local_unnamed_addr #0 {
entry:
%shl = shl i32 %a, 4
%and = and i32 %shl, 4080
ret i32 %and
}
; Function Attrs: norecurse nounwind readnone
define zeroext i32 @testRLWINMFullReg(i32 zeroext %a) local_unnamed_addr #0 {
entry:
%shl = shl i32 %a, 4
%and = and i32 %shl, 4080
ret i32 %and
}
; Function Attrs: norecurse nounwind readnone
define zeroext i32 @testRLWINMFullRegOutOfRange(i32 zeroext %a) local_unnamed_addr #0 {
entry:
%shl = shl i32 %a, 4
%and = and i32 %shl, 4080
ret i32 %and
}
; Function Attrs: norecurse nounwind readnone
define i64 @testRLWINM8(i64 %a) local_unnamed_addr #0 {
entry:
%shl = shl i64 %a, 4
%and = and i64 %shl, 4080
ret i64 %and
}
; Function Attrs: norecurse nounwind readnone
define zeroext i32 @testRLWINMo(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
entry:
%and = and i32 %a, 255
%tobool = icmp eq i32 %and, 0
%cond = select i1 %tobool, i32 %b, i32 %a
ret i32 %cond
}
; Function Attrs: norecurse nounwind readnone
define zeroext i32 @testRLWINMo2(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
entry:
%and = and i32 %a, 255
%tobool = icmp eq i32 %and, 0
%cond = select i1 %tobool, i32 %b, i32 %a
ret i32 %cond
}
; Function Attrs: norecurse nounwind readnone
define i64 @testRLWINM8o(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%a.tr = trunc i64 %a to i32
%0 = shl i32 %a.tr, 4
%conv = and i32 %0, 4080
%tobool = icmp eq i32 %conv, 0
%conv1 = zext i32 %conv to i64
%cond = select i1 %tobool, i64 %b, i64 %conv1
ret i64 %cond
}
; Function Attrs: norecurse nounwind readnone
define i64 @testSLD(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%shl = shl i64 %a, %b
ret i64 %shl
}
; Function Attrs: norecurse nounwind readnone
define i64 @testSLDo(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%shl = shl i64 %a, %b
%tobool = icmp eq i64 %shl, 0
%cond = select i1 %tobool, i64 %b, i64 %a
ret i64 %cond
}
; Function Attrs: norecurse nounwind readnone
define i64 @testSRD(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%shr = lshr i64 %a, %b
ret i64 %shr
}
; Function Attrs: norecurse nounwind readnone
define i64 @testSRDo(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%shr = lshr i64 %a, %b
%tobool = icmp eq i64 %shr, 0
%cond = select i1 %tobool, i64 %b, i64 %a
ret i64 %cond
}
; Function Attrs: norecurse nounwind readnone
define zeroext i32 @testSLW(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
entry:
%shl = shl i32 %a, %b
ret i32 %shl
}
; Function Attrs: norecurse nounwind readnone
define zeroext i32 @testSLWo(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
entry:
%shl = shl i32 %a, %b
%tobool = icmp eq i32 %shl, 0
%cond = select i1 %tobool, i32 %b, i32 %a
ret i32 %cond
}
; Function Attrs: norecurse nounwind readnone
define zeroext i32 @testSRW(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
entry:
%shr = lshr i32 %a, %b
ret i32 %shr
}
; Function Attrs: norecurse nounwind readnone
define zeroext i32 @testSRWo(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
entry:
%shr = lshr i32 %a, %b
%tobool = icmp eq i32 %shr, 0
%cond = select i1 %tobool, i32 %b, i32 %a
ret i32 %cond
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @testSRAW(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
entry:
%shr = ashr i32 %a, %b
ret i32 %shr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @testSRAWo(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
entry:
%shr = ashr i32 %a, %b
%tobool = icmp eq i32 %shr, 0
%cond = select i1 %tobool, i32 %b, i32 %shr
ret i32 %cond
}
; Function Attrs: norecurse nounwind readnone
define i64 @testSRAD(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%shr = ashr i64 %a, %b
ret i64 %shr
}
; Function Attrs: norecurse nounwind readnone
define i64 @testSRADo(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%shr = ashr i64 %a, %b
%tobool = icmp eq i64 %shr, 0
%cond = select i1 %tobool, i64 %b, i64 %shr
ret i64 %cond
}
; Function Attrs: norecurse nounwind
define void @testSTBUX(i8* nocapture %ptr, i8 zeroext %a, i32 zeroext %idx) local_unnamed_addr #3 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds i8, i8* %ptr, i64 %idxprom
store i8 %a, i8* %arrayidx, align 1, !tbaa !3
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds i8, i8* %ptr, i64 %idxprom2
store i8 %a, i8* %arrayidx3, align 1, !tbaa !3
ret void
}
; Function Attrs: norecurse nounwind
define void @testSTBX(i8* nocapture %ptr, i8 zeroext %a, i32 zeroext %idx) local_unnamed_addr #3 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds i8, i8* %ptr, i64 %idxprom
store i8 %a, i8* %arrayidx, align 1, !tbaa !3
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds i8, i8* %ptr, i64 %idxprom2
store i8 %a, i8* %arrayidx3, align 1, !tbaa !3
ret void
}
; Function Attrs: norecurse nounwind
define void @testSTHUX(i16* nocapture %ptr, i16 zeroext %a, i32 zeroext %idx) local_unnamed_addr #3 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds i16, i16* %ptr, i64 %idxprom
store i16 %a, i16* %arrayidx, align 2, !tbaa !6
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds i16, i16* %ptr, i64 %idxprom2
store i16 %a, i16* %arrayidx3, align 2, !tbaa !6
ret void
}
; Function Attrs: norecurse nounwind
define void @testSTHX(i16* nocapture %ptr, i16 zeroext %a, i32 zeroext %idx) local_unnamed_addr #3 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds i16, i16* %ptr, i64 %idxprom
store i16 %a, i16* %arrayidx, align 1, !tbaa !3
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds i16, i16* %ptr, i64 %idxprom2
store i16 %a, i16* %arrayidx3, align 1, !tbaa !3
ret void
}
; Function Attrs: norecurse nounwind
define void @testSTWUX(i32* nocapture %ptr, i32 zeroext %a, i32 zeroext %idx) local_unnamed_addr #3 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds i32, i32* %ptr, i64 %idxprom
store i32 %a, i32* %arrayidx, align 4, !tbaa !8
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds i32, i32* %ptr, i64 %idxprom2
store i32 %a, i32* %arrayidx3, align 4, !tbaa !8
ret void
}
; Function Attrs: norecurse nounwind
define void @testSTWX(i32* nocapture %ptr, i32 zeroext %a, i32 zeroext %idx) local_unnamed_addr #3 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds i32, i32* %ptr, i64 %idxprom
store i32 %a, i32* %arrayidx, align 4, !tbaa !8
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds i32, i32* %ptr, i64 %idxprom2
store i32 %a, i32* %arrayidx3, align 4, !tbaa !8
ret void
}
; Function Attrs: norecurse nounwind
define void @testSTDUX(i64* nocapture %ptr, i64 %a, i32 zeroext %idx) local_unnamed_addr #3 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds i64, i64* %ptr, i64 %idxprom
store i64 %a, i64* %arrayidx, align 8, !tbaa !10
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds i64, i64* %ptr, i64 %idxprom2
store i64 %a, i64* %arrayidx3, align 8, !tbaa !10
ret void
}
; Function Attrs: norecurse nounwind
define void @testSTDX(i64* nocapture %ptr, i64 %a, i32 zeroext %idx) local_unnamed_addr #3 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds i64, i64* %ptr, i64 %idxprom
store i64 %a, i64* %arrayidx, align 8, !tbaa !10
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds i64, i64* %ptr, i64 %idxprom2
store i64 %a, i64* %arrayidx3, align 8, !tbaa !10
ret void
}
; Function Attrs: norecurse nounwind readonly
define void @testSTFSX(float* nocapture %ptr, float %a, i32 zeroext %idx) local_unnamed_addr #2 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds float, float* %ptr, i64 %idxprom
store float %a, float* %arrayidx, align 4, !tbaa !14
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds float, float* %ptr, i64 %idxprom2
store float %a, float* %arrayidx3, align 4, !tbaa !14
ret void
}
; Function Attrs: norecurse nounwind readonly
define void @testSTFSUX(float* nocapture %ptr, float %a, i32 zeroext %idx) local_unnamed_addr #2 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds float, float* %ptr, i64 %idxprom
store float %a, float* %arrayidx, align 4, !tbaa !14
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds float, float* %ptr, i64 %idxprom2
store float %a, float* %arrayidx3, align 4, !tbaa !14
ret void
}
; Function Attrs: norecurse nounwind readonly
define void @testSTFDX(double* nocapture %ptr, double %a, i32 zeroext %idx) local_unnamed_addr #2 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds double, double* %ptr, i64 %idxprom
store double %a, double* %arrayidx, align 8, !tbaa !12
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds double, double* %ptr, i64 %idxprom2
store double %a, double* %arrayidx3, align 8, !tbaa !12
ret void
}
; Function Attrs: norecurse nounwind readonly
define void @testSTFDUX(double* nocapture %ptr, double %a, i32 zeroext %idx) local_unnamed_addr #2 {
entry:
%add = add i32 %idx, 1
%idxprom = zext i32 %add to i64
%arrayidx = getelementptr inbounds double, double* %ptr, i64 %idxprom
store double %a, double* %arrayidx, align 8, !tbaa !12
%add1 = add i32 %idx, 2
%idxprom2 = zext i32 %add1 to i64
%arrayidx3 = getelementptr inbounds double, double* %ptr, i64 %idxprom2
store double %a, double* %arrayidx3, align 8, !tbaa !12
ret void
}
; Function Attrs: norecurse nounwind
define void @testSTXSSPX(float* nocapture %ptr, float %a, i32 zeroext %idx) local_unnamed_addr #3 {
entry:
%idxprom = zext i32 %idx to i64
%arrayidx = getelementptr inbounds float, float* %ptr, i64 %idxprom
store float %a, float* %arrayidx, align 4, !tbaa !14
ret void
}
; Function Attrs: norecurse nounwind
define void @testSTXSDX(double* nocapture %ptr, double %a, i32 zeroext %idx) local_unnamed_addr #3 {
entry:
%idxprom = zext i32 %idx to i64
%arrayidx = getelementptr inbounds double, double* %ptr, i64 %idxprom
store double %a, double* %arrayidx, align 8, !tbaa !12
ret void
}
; Function Attrs: norecurse nounwind
define void @testSTXVX(<4 x i32>* nocapture %ptr, <4 x i32> %a, i32 zeroext %idx) local_unnamed_addr #3 {
entry:
%idxprom = zext i32 %idx to i64
%arrayidx = getelementptr inbounds <4 x i32>, <4 x i32>* %ptr, i64 %idxprom
store <4 x i32> %a, <4 x i32>* %arrayidx, align 16, !tbaa !3
ret void
}
; Function Attrs: norecurse nounwind readnone
define i128 @testSUBFC(i128 %a, i128 %b) local_unnamed_addr #0 {
entry:
%sub = sub nsw i128 %a, %b
ret i128 %sub
}
; Function Attrs: norecurse nounwind readnone
define i128 @testSUBFC8(i128 %a, i128 %b) local_unnamed_addr #0 {
entry:
%sub = sub nsw i128 %a, %b
ret i128 %sub
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @testXOR(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
entry:
%xor = xor i32 %b, %a
ret i32 %xor
}
; Function Attrs: norecurse nounwind readnone
define i64 @testXOR8(i64 %a, i64 %b) local_unnamed_addr #0 {
entry:
%xor = xor i64 %b, %a
ret i64 %xor
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @testXORI(i32 signext %a) local_unnamed_addr #0 {
entry:
%xor = xor i32 %a, 17
ret i32 %xor
}
; Function Attrs: norecurse nounwind readnone
define i64 @testXOR8I(i64 %a) local_unnamed_addr #0 {
entry:
%xor = xor i64 %a, 17
ret i64 %xor
}
attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { norecurse nounwind readonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #2 = { norecurse nounwind readonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,-vsx,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #3 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
!llvm.module.flags = !{!0, !1}
!llvm.ident = !{!2}
!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 7, !"PIC Level", i32 2}
!2 = !{!"clang version 6.0.0 (trunk 316067)"}
!3 = !{!4, !4, i64 0}
!4 = !{!"omnipotent char", !5, i64 0}
!5 = !{!"Simple C/C++ TBAA"}
!6 = !{!7, !7, i64 0}
!7 = !{!"short", !4, i64 0}
!8 = !{!9, !9, i64 0}
!9 = !{!"int", !4, i64 0}
!10 = !{!11, !11, i64 0}
!11 = !{!"long long", !4, i64 0}
!12 = !{!13, !13, i64 0}
!13 = !{!"double", !4, i64 0}
!14 = !{!15, !15, i64 0}
!15 = !{!"float", !4, i64 0}
...
---
name: testADD4
# CHECK-ALL: name: testADD4
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc, preferred-register: '' }
- { id: 1, class: g8rc, preferred-register: '' }
- { id: 2, class: gprc, preferred-register: '' }
- { id: 3, class: gprc, preferred-register: '' }
- { id: 4, class: gprc_and_gprc_nor0, preferred-register: '' }
- { id: 5, class: gprc, preferred-register: '' }
- { id: 6, class: g8rc, preferred-register: '' }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
- { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: $x3, $x4
%1 = COPY $x4
%0 = COPY $x3
%2 = LI 33
%3 = COPY %0.sub_32
%4 = ADD4 killed %3, %2
%5 = ADD4 killed %2, killed %4
; CHECK: ADDI killed %3, 33
; CHECK: ADDI killed %4, 33
; CHECK-LATE: addi 3, 3, 33
; CHECK-LATE: addi 3, 3, 33
%6 = EXTSW_32_64 killed %5
$x3 = COPY %6
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
name: testADD8
# CHECK-ALL: name: testADD8
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc, preferred-register: '' }
- { id: 1, class: g8rc, preferred-register: '' }
- { id: 2, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 3, class: g8rc, preferred-register: '' }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
- { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: $x3, $x4
%1 = LI8 33
%0 = COPY $x3
%2 = ADD8 %0, %1
%3 = ADD8 killed %1, killed %2
; CHECK: ADDI8 %0, 33
; CHECK: ADDI8 killed %2, 33
; CHECK-LATE: addi 3, 3, 33
; CHECK-LATE: addi 3, 3, 33
$x3 = COPY %3
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
name: testADDC
# CHECK-ALL: name: testADDC
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc, preferred-register: '' }
- { id: 1, class: g8rc, preferred-register: '' }
- { id: 2, class: g8rc, preferred-register: '' }
- { id: 3, class: g8rc, preferred-register: '' }
- { id: 4, class: gprc, preferred-register: '' }
- { id: 5, class: gprc, preferred-register: '' }
- { id: 6, class: gprc, preferred-register: '' }
- { id: 7, class: g8rc, preferred-register: '' }
- { id: 8, class: g8rc, preferred-register: '' }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
- { reg: '$x4', virtual-reg: '%1' }
- { reg: '$x5', virtual-reg: '%2' }
- { reg: '$x6', virtual-reg: '%3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: $x3, $x4, $x5, $x6
%3 = COPY $x6
%2 = COPY $x5
%1 = COPY $x4
%0 = COPY $x3
%4 = COPY %0.sub_32
%5 = LI 55
%6 = ADDC %5, %4, implicit-def $carry
; CHECK: ADDIC %4, 55, implicit-def $carry
; CHECK-LATE: addic 3, 3, 55
%7 = ADDE8 %3, %1, implicit-def dead $carry, implicit $carry
%8 = EXTSW_32_64 %6
$x3 = COPY %8
$x4 = COPY %7
BLR8 implicit $lr8, implicit $rm, implicit $x3, implicit $x4
...
---
name: testADDC8
# CHECK-ALL: name: testADDC8
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc, preferred-register: '' }
- { id: 1, class: g8rc, preferred-register: '' }
- { id: 2, class: g8rc, preferred-register: '' }
- { id: 3, class: g8rc, preferred-register: '' }
- { id: 4, class: g8rc, preferred-register: '' }
- { id: 5, class: g8rc, preferred-register: '' }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
- { reg: '$x4', virtual-reg: '%1' }
- { reg: '$x5', virtual-reg: '%2' }
- { reg: '$x6', virtual-reg: '%3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: $x3, $x4, $x5, $x6
%3 = COPY $x6
%2 = COPY $x5
%1 = COPY $x4
%0 = LI8 777
%4 = ADDC8 %2, %0, implicit-def $carry
; CHECK: ADDIC8 %2, 777, implicit-def $carry
; CHECK-LATE: addic 3, 5, 777
%5 = ADDE8 %3, %1, implicit-def dead $carry, implicit $carry
$x3 = COPY %4
$x4 = COPY %5
BLR8 implicit $lr8, implicit $rm, implicit $x3, implicit $x4
...
---
name: testADDCo
# CHECK-ALL: name: testADDCo
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc, preferred-register: '' }
- { id: 1, class: gprc, preferred-register: '' }
- { id: 2, class: gprc, preferred-register: '' }
- { id: 3, class: gprc, preferred-register: '' }
- { id: 4, class: crrc, preferred-register: '' }
- { id: 5, class: crbitrc, preferred-register: '' }
- { id: 6, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 7, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 8, class: g8rc, preferred-register: '' }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
- { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: $x3, $x4
%1 = LI 433
%0 = COPY $x3
%2 = COPY %0.sub_32
%3 = ADDCo %1, %2, implicit-def $cr0, implicit-def $carry
; CHECK: ADDICo %2, 433, implicit-def $cr0, implicit-def $carry
; CHECK-LATE: addic. 3, 3, 433
%4 = COPY killed $cr0
%5 = COPY %4.sub_eq
%6 = LI8 0
%7 = LI8 -1
%8 = ISEL8 %7, %6, %5
$x3 = COPY %8
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
name: testADDI
# CHECK-ALL: name: testADDI
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc, preferred-register: '' }
- { id: 1, class: gprc_and_gprc_nor0, preferred-register: '' }
- { id: 2, class: gprc, preferred-register: '' }
- { id: 3, class: g8rc, preferred-register: '' }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: $x3
%0 = COPY $x3
%1 = LI 77
%2 = ADDI killed %1, 44
%3 = EXTSW_32_64 killed %2
; CHECK: LI 121
; CHECK-LATE: li 3, 121
$x3 = COPY %3
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
name: testADDI8
# CHECK-ALL: name: testADDI8
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc, preferred-register: '' }
- { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 2, class: g8rc, preferred-register: '' }
- { id: 3, class: g8rc, preferred-register: '' }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: $x3
%0 = COPY $x3
%1 = LI8 333
%2 = ADDI8 killed %1, 44
; CHECK: LI8 377
; CHECK-LATE: li 3, 377
%3 = EXTSW killed %2
$x3 = COPY %3
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
name: testANDo
# CHECK-ALL: name: testANDo
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 1, class: gprc, preferred-register: '' }
- { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' }
- { id: 3, class: gprc, preferred-register: '' }
- { id: 4, class: crrc, preferred-register: '' }
- { id: 5, class: gprc, preferred-register: '' }
- { id: 6, class: g8rc, preferred-register: '' }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
- { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: $x3, $x4
%1 = LI 78
%0 = COPY $x3
%2 = COPY %0.sub_32
%3 = ANDo %1, %2, implicit-def $cr0
; CHECK: ANDIo %2, 78, implicit-def $cr0
; CHECK-LATE: andi. 5, 3, 78
%4 = COPY killed $cr0
%5 = ISEL %2, %1, %4.sub_eq
%6 = EXTSW_32_64 killed %5
$x3 = COPY %6
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
name: testAND8o
# CHECK-ALL: name: testAND8o
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 1, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 2, class: g8rc, preferred-register: '' }
- { id: 3, class: crrc, preferred-register: '' }
- { id: 4, class: g8rc, preferred-register: '' }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
- { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: $x3, $x4
%1 = LI8 321
%0 = COPY $x3
%2 = AND8o %1, %0, implicit-def $cr0
; CHECK: ANDIo8 %0, 321, implicit-def $cr0
; CHECK-LATE: andi. 5, 3, 321
%3 = COPY killed $cr0
%4 = ISEL8 %1, %0, %3.sub_eq
$x3 = COPY %4
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
name: testCMPD
# CHECK-ALL: name: testCMPD
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 1, class: g8rc, preferred-register: '' }
- { id: 2, class: crrc, preferred-register: '' }
- { id: 3, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 4, class: g8rc, preferred-register: '' }
- { id: 5, class: g8rc, preferred-register: '' }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
- { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: $x3, $x4
%1 = LI8 65533
%0 = COPY $x3
%2 = CMPD %0, %1
; CHECK: CMPDI %0, -3
; CHECK-LATE: cmpdi 3, -3
%4 = ISEL8 $zero8, %0, %2.sub_gt
%5 = ADD8 killed %4, %1
$x3 = COPY %5
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
name: testCMPDI
# CHECK-ALL: name: testCMPDI
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 1, class: g8rc, preferred-register: '' }
- { id: 2, class: crrc, preferred-register: '' }
- { id: 3, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 4, class: g8rc, preferred-register: '' }
- { id: 5, class: g8rc, preferred-register: '' }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
- { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: $x3, $x4
%1 = COPY $x4
%0 = LI8 89
%2 = CMPDI %0, 87
%4 = ISEL8 $zero8, %0, %2.sub_gt
; CHECK: LI8 0
%5 = ADD8 killed %4, %1
$x3 = COPY %5
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
name: testCMPDI_F
# CHECK-ALL: name: testCMPDI_F
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 1, class: g8rc, preferred-register: '' }
- { id: 2, class: crrc, preferred-register: '' }
- { id: 3, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 4, class: g8rc, preferred-register: '' }
- { id: 5, class: g8rc, preferred-register: '' }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
- { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: $x3, $x4
%1 = COPY $x4
%0 = LI8 87
%2 = CMPDI %0, 87
%4 = ISEL8 $zero8, %0, %2.sub_gt
; CHECK: COPY %0
%5 = ADD8 killed %4, %1
$x3 = COPY %5
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
name: testCMPLD
# CHECK-ALL: name: testCMPLD
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 1, class: g8rc, preferred-register: '' }
- { id: 2, class: crrc, preferred-register: '' }
- { id: 3, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 4, class: g8rc, preferred-register: '' }
- { id: 5, class: g8rc, preferred-register: '' }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
- { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: $x3, $x4
%1 = LI8 99
%0 = COPY $x3
%2 = CMPLD %0, %1
; CHECK: CMPLDI %0, 99
; CHECK-LATE: cmpldi 3, 99
%4 = ISEL8 $zero8, %0, %2.sub_gt
%5 = ADD8 killed %4, %1
$x3 = COPY %5
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
name: testCMPLDI
# CHECK-ALL: name: testCMPLDI
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 1, class: g8rc, preferred-register: '' }
- { id: 2, class: crrc, preferred-register: '' }
- { id: 3, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 4, class: g8rc, preferred-register: '' }
- { id: 5, class: g8rc, preferred-register: '' }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
- { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: $x3, $x4
%1 = COPY $x4
%0 = LI8 65534
%2 = CMPLDI %0, 65535
%4 = ISEL8 $zero8, %0, %2.sub_gt
; CHECK: COPY %0
%5 = ADD8 killed %4, %1
$x3 = COPY %5
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
name: testCMPW
# CHECK-ALL: name: testCMPW
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc, preferred-register: '' }
- { id: 1, class: g8rc, preferred-register: '' }
- { id: 2, class: gprc, preferred-register: '' }
- { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' }
- { id: 4, class: crrc, preferred-register: '' }
- { id: 5, class: gprc_and_gprc_nor0, preferred-register: '' }
- { id: 6, class: gprc, preferred-register: '' }
- { id: 7, class: gprc, preferred-register: '' }
- { id: 8, class: g8rc, preferred-register: '' }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
- { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: $x3, $x4
%1 = COPY $x4
%0 = COPY $x3
%2 = LI -1
%3 = COPY %0.sub_32
%4 = CMPW %3, %2
; CHECK: CMPWI %3, -1
%6 = ISEL $zero, %3, %4.sub_gt
%7 = ADD4 killed %6, %2
%8 = EXTSW_32_64 killed %7
$x3 = COPY %8
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
name: testCMPWI
# CHECK-ALL: name: testCMPWI
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc, preferred-register: '' }
- { id: 1, class: g8rc, preferred-register: '' }
- { id: 2, class: gprc, preferred-register: '' }
- { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' }
- { id: 4, class: crrc, preferred-register: '' }
- { id: 5, class: gprc_and_gprc_nor0, preferred-register: '' }
- { id: 6, class: gprc, preferred-register: '' }
- { id: 7, class: gprc, preferred-register: '' }
- { id: 8, class: g8rc, preferred-register: '' }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
- { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: $x3, $x4
%1 = COPY $x4
%0 = COPY $x3
%2 = COPY %1.sub_32
%3 = LI -3
%4 = CMPWI %3, 87
%6 = ISEL $zero, %3, %4.sub_gt
; CHECK: COPY %3
%7 = ADD4 killed %6, killed %2
%8 = EXTSW_32_64 killed %7
$x3 = COPY %8
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
name: testCMPLW
# CHECK-ALL: name: testCMPLW
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc, preferred-register: '' }
- { id: 1, class: g8rc, preferred-register: '' }
- { id: 2, class: gprc, preferred-register: '' }
- { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' }
- { id: 4, class: crrc, preferred-register: '' }
- { id: 5, class: gprc_and_gprc_nor0, preferred-register: '' }
- { id: 6, class: gprc, preferred-register: '' }
- { id: 7, class: gprc, preferred-register: '' }
- { id: 8, class: g8rc, preferred-register: '' }
- { id: 9, class: g8rc, preferred-register: '' }
- { id: 10, class: g8rc, preferred-register: '' }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
- { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: $x3, $x4
%1 = COPY $x4
%0 = COPY $x3
%2 = LI 32767
%3 = COPY %0.sub_32
%4 = CMPLW %3, %2
; CHECK: CMPLWI %3, 32767
; CHECK-LATE: cmplwi 3, 32767
%6 = ISEL $zero, %3, %4.sub_gt
%7 = ADD4 killed %6, %2
%9 = IMPLICIT_DEF
%8 = INSERT_SUBREG %9, killed %7, 1
%10 = RLDICL killed %8, 0, 32
$x3 = COPY %10
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
name: testCMPLWI
# CHECK-ALL: name: testCMPLWI
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc, preferred-register: '' }
- { id: 1, class: g8rc, preferred-register: '' }
- { id: 2, class: gprc, preferred-register: '' }
- { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' }
- { id: 4, class: crrc, preferred-register: '' }
- { id: 5, class: gprc_and_gprc_nor0, preferred-register: '' }
- { id: 6, class: gprc, preferred-register: '' }
- { id: 7, class: gprc, preferred-register: '' }
- { id: 8, class: g8rc, preferred-register: '' }
- { id: 9, class: g8rc, preferred-register: '' }
- { id: 10, class: g8rc, preferred-register: '' }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
- { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: $x3, $x4
%1 = COPY $x4
%0 = COPY $x3
%2 = COPY %1.sub_32
%3 = LI -3
%4 = CMPLWI %3, 87
%6 = ISEL $zero, %3, %4.sub_gt
; CHECK: LI 0
%7 = ADD4 killed %6, killed %2
%9 = IMPLICIT_DEF
%8 = INSERT_SUBREG %9, killed %7, 1
%10 = RLDICL killed %8, 0, 32
$x3 = COPY %10
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
name: testLBZUX
# CHECK-ALL: name: testLBZUX
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 1, class: g8rc, preferred-register: '' }
- { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' }
- { id: 3, class: gprc, preferred-register: '' }
- { id: 4, class: g8rc, preferred-register: '' }
- { id: 5, class: g8rc, preferred-register: '' }
- { id: 6, class: g8rc, preferred-register: '' }
- { id: 7, class: gprc, preferred-register: '' }
- { id: 8, class: gprc, preferred-register: '' }
- { id: 9, class: g8rc, preferred-register: '' }
- { id: 10, class: g8rc, preferred-register: '' }
- { id: 11, class: g8rc, preferred-register: '' }
- { id: 12, class: gprc, preferred-register: '' }
- { id: 13, class: gprc, preferred-register: '' }
- { id: 14, class: g8rc, preferred-register: '' }
- { id: 15, class: g8rc, preferred-register: '' }
- { id: 16, class: g8rc, preferred-register: '' }
- { id: 17, class: g8rc_and_g8rc_nox0, preferred-register: '' }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
- { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: $x3, $x4
%1 = COPY $x4
%0 = COPY $x3
%2 = COPY %1.sub_32
%3 = ADDI %2, 1
%5 = IMPLICIT_DEF
%4 = INSERT_SUBREG %5, killed %3, 1
%6 = RLDICL killed %4, 0, 32
%7 = LBZX %0, killed %6 :: (load 1 from %ir.arrayidx, !tbaa !3)
%8 = ADDI %2, 2
%10 = IMPLICIT_DEF
%9 = INSERT_SUBREG %10, killed %8, 1
%11 = LI8 -15
%12,%17 = LBZUX %0, killed %11 :: (load 1 from %ir.arrayidx3, !tbaa !3)
; CHECK: LBZU -15, %0
; CHECK-LATE: lbzu 5, -15(3)
%13 = ADD4 killed %12, killed %7
%15 = IMPLICIT_DEF
%14 = INSERT_SUBREG %15, killed %13, 1
%16 = RLWINM8 killed %14, 0, 24, 31
$x3 = COPY %16
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
name: testLBZX
# CHECK-ALL: name: testLBZX
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 1, class: g8rc, preferred-register: '' }
- { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' }
- { id: 3, class: gprc, preferred-register: '' }
- { id: 4, class: g8rc, preferred-register: '' }
- { id: 5, class: g8rc, preferred-register: '' }
- { id: 6, class: g8rc, preferred-register: '' }
- { id: 7, class: gprc, preferred-register: '' }
- { id: 8, class: gprc, preferred-register: '' }
- { id: 9, class: g8rc, preferred-register: '' }
- { id: 10, class: g8rc, preferred-register: '' }
- { id: 11, class: g8rc, preferred-register: '' }
- { id: 12, class: gprc, preferred-register: '' }
- { id: 13, class: gprc, preferred-register: '' }
- { id: 14, class: g8rc, preferred-register: '' }
- { id: 15, class: g8rc, preferred-register: '' }
- { id: 16, class: g8rc, preferred-register: '' }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
- { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: $x3, $x4
%1 = COPY $x4
%0 = LI8 45
%2 = COPY %1.sub_32
%3 = ADDI %2, 1
%5 = IMPLICIT_DEF
%4 = INSERT_SUBREG %5, killed %3, 1
%6 = RLDICL killed %4, 0, 32
%7 = LBZX %0, killed %6 :: (load 1 from %ir.arrayidx, !tbaa !3)
; CHECK: LBZ 45, killed %6
; CHECK-LATE: lbz 5, 45(5)
%8 = ADDI %2, 2
%10 = IMPLICIT_DEF
%9 = INSERT_SUBREG %10, killed %8, 1
%11 = RLDICL killed %9, 0, 32
%12 = LBZX %0, killed %11 :: (load 1 from %ir.arrayidx3, !tbaa !3)
; CHECK: LBZ 45, killed %11
; CHECK-LATE: lbz 3, 45(4)
%13 = ADD4 killed %12, killed %7
%15 = IMPLICIT_DEF
%14 = INSERT_SUBREG %15, killed %13, 1
%16 = RLWINM8 killed %14, 0, 24, 31
$x3 = COPY %16
BLR8 implicit $lr8, implicit $rm, implicit $x3
...
---
name: testLHZUX
# CHECK-ALL: name: testLHZUX
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc_and_g8rc_nox0, preferred-register: '' }
- { id: 1, class: g8rc, preferred-register: '' }
- { id: 2, class: gprc_and_gprc_nor0, preferred-register: '' }
- { id: 3, class: gprc, preferred-register: '' }
- { id: 4, class: g8rc, preferred-register: '' }
- { id: 5, class: g8rc, preferred-register: '' }
- { id: 6, class: g8rc, preferred-register: '' }
- { id: 7, class: gprc, preferred-register: '' }
- { id: 8, class: gprc, preferred-register: '' }
- { id: 9, class: g8rc, preferred-register: '' }
- { id: 10, class: g8rc, preferred-register: '' }
- { id: 11, class: g8rc, preferred-register: '' }
- { id: 12, class: gprc, preferred-register: '' }
- { id: 13, class: gprc, preferred-register: '' }
- { id: 14, class: g8rc, preferred-register: '' }
- { id: 15, class: g8rc, preferred-register: '' }
- { id: 16, class: g8rc, preferred-register: '' }
- { id: 17, class: g8rc_and_g8rc_nox0, preferred-register: '' }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
- { reg: '$x4', virtual-reg: '%1' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 4294967295
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
bb.0.entry:
liveins: $x3, $x4
%1 = COPY $x4
%0 = COPY $x3
%2 = COPY %1.sub_32
%3 = ADDI %2, 1
%5 = IMPLICIT_DEF
%4 = INSERT_SUBREG %5, killed %3, 1
%6 = RLDIC killed %4, 1, 31
%7 = LHZX %0, killed %6 :: (load 2 from %ir.arrayidx, !tbaa !6)
%8 = ADDI %2, 2
%10 = IMPLICIT_DEF
%9 = INSERT_SUBREG %10