| ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs -o - %s | FileCheck %s |
| ; FIXME: Test with SI when argument lowering not broken for f16 |
| |
| ; Natural mapping |
| define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 |
| ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: S_ENDPGM 0 |
| call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) |
| ret void |
| } |
| |
| ; Copies for VGPR arguments |
| define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__sgpr_val__sgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, float inreg %val, i32 inreg %voffset, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__sgpr_val__sgpr_voffset__sgpr_soffset |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8 |
| ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; CHECK: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; CHECK: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7 |
| ; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr8 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] |
| ; CHECK: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] |
| ; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY7]], [[COPY8]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: S_ENDPGM 0 |
| call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) |
| ret void |
| } |
| |
| ; Waterfall for rsrc |
| define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset(<4 x i32> %rsrc, float %val, i32 %voffset, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: successors: %bb.2(0x80000000) |
| ; CHECK: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 |
| ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 |
| ; CHECK: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5 |
| ; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1 |
| ; CHECK: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3 |
| ; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec |
| ; CHECK: bb.2: |
| ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000) |
| ; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec |
| ; CHECK: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec |
| ; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 |
| ; CHECK: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY7]], implicit $exec |
| ; CHECK: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub0, implicit $exec |
| ; CHECK: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub1, implicit $exec |
| ; CHECK: [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1 |
| ; CHECK: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY8]], implicit $exec |
| ; CHECK: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc |
| ; CHECK: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 |
| ; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE3]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec |
| ; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc |
| ; CHECK: S_CBRANCH_EXECNZ %bb.2, implicit $exec |
| ; CHECK: bb.3: |
| ; CHECK: successors: %bb.4(0x80000000) |
| ; CHECK: $exec = S_MOV_B64_term [[S_MOV_B64_term]] |
| ; CHECK: bb.4: |
| ; CHECK: S_ENDPGM 0 |
| call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) |
| ret void |
| } |
| |
| ; Waterfall for soffset |
| define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__vgpr_soffset(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__vgpr_soffset |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: successors: %bb.2(0x80000000) |
| ; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2 |
| ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec |
| ; CHECK: bb.2: |
| ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000) |
| ; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec |
| ; CHECK: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_]], [[COPY6]], implicit $exec |
| ; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[V_READFIRSTLANE_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[V_CMP_EQ_U32_e64_]], implicit-def $exec, implicit-def $scc, implicit $exec |
| ; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc |
| ; CHECK: S_CBRANCH_EXECNZ %bb.2, implicit $exec |
| ; CHECK: bb.3: |
| ; CHECK: successors: %bb.4(0x80000000) |
| ; CHECK: $exec = S_MOV_B64_term [[S_MOV_B64_term]] |
| ; CHECK: bb.4: |
| ; CHECK: S_ENDPGM 0 |
| call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) |
| ret void |
| } |
| |
| ; Waterfall for rsrc and soffset |
| define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__vgpr_soffset(<4 x i32> %rsrc, float %val, i32 %voffset, i32 %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__vgpr_soffset |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: successors: %bb.2(0x80000000) |
| ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 |
| ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 |
| ; CHECK: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5 |
| ; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1 |
| ; CHECK: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3 |
| ; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec |
| ; CHECK: bb.2: |
| ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000) |
| ; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec |
| ; CHECK: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec |
| ; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 |
| ; CHECK: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY7]], implicit $exec |
| ; CHECK: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub0, implicit $exec |
| ; CHECK: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub1, implicit $exec |
| ; CHECK: [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1 |
| ; CHECK: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY8]], implicit $exec |
| ; CHECK: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc |
| ; CHECK: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 |
| ; CHECK: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec |
| ; CHECK: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY6]], implicit $exec |
| ; CHECK: [[S_AND_B64_1:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U32_e64_]], [[S_AND_B64_]], implicit-def $scc |
| ; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE3]], [[V_READFIRSTLANE_B32_4]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_1]], implicit-def $exec, implicit-def $scc, implicit $exec |
| ; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc |
| ; CHECK: S_CBRANCH_EXECNZ %bb.2, implicit $exec |
| ; CHECK: bb.3: |
| ; CHECK: successors: %bb.4(0x80000000) |
| ; CHECK: $exec = S_MOV_B64_term [[S_MOV_B64_term]] |
| ; CHECK: bb.4: |
| ; CHECK: S_ENDPGM 0 |
| call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) |
| ret void |
| } |
| |
| define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 |
| ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: S_ENDPGM 0 |
| call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 1) |
| ret void |
| } |
| |
| define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_slc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_slc |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 |
| ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 1, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: S_ENDPGM 0 |
| call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 2) |
| ret void |
| } |
| |
| define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_slc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_slc |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 |
| ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 1, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: S_ENDPGM 0 |
| call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 3) |
| ret void |
| } |
| |
| define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_dlc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_dlc |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 |
| ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 1, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: S_ENDPGM 0 |
| call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 4) |
| ret void |
| } |
| |
| define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_slc_dlc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_slc_dlc |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 |
| ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 1, 0, 1, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: S_ENDPGM 0 |
| call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 6) |
| ret void |
| } |
| |
| define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_dlc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_dlc |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 |
| ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 0, 0, 1, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: S_ENDPGM 0 |
| call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 5) |
| ret void |
| } |
| |
| define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_slc_dlc(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_slc_dlc |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 |
| ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 1, 0, 1, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: S_ENDPGM 0 |
| call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 7) |
| ret void |
| } |
| |
| define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32(<4 x i32> inreg %rsrc, <2 x float> %val, i32 %voffset, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32 |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 |
| ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 |
| ; CHECK: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 |
| ; CHECK: BUFFER_STORE_DWORDX2_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: S_ENDPGM 0 |
| call void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) |
| ret void |
| } |
| |
| define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v3f32(<4 x i32> inreg %rsrc, <3 x float> %val, i32 %voffset, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v3f32 |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 |
| ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 |
| ; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 |
| ; CHECK: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2 |
| ; CHECK: BUFFER_STORE_DWORDX3_OFFEN_exact [[REG_SEQUENCE1]], [[COPY7]], [[REG_SEQUENCE]], [[COPY8]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 12 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: S_ENDPGM 0 |
| call void @llvm.amdgcn.raw.buffer.store.v3f32(<3 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) |
| ret void |
| } |
| |
| define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32(<4 x i32> inreg %rsrc, <4 x float> %val, i32 %voffset, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32 |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 |
| ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 |
| ; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 |
| ; CHECK: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 |
| ; CHECK: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 |
| ; CHECK: BUFFER_STORE_DWORDX4_OFFEN_exact [[REG_SEQUENCE1]], [[COPY8]], [[REG_SEQUENCE]], [[COPY9]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 16 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: S_ENDPGM 0 |
| call void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) |
| ret void |
| } |
| |
| define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_i8(<4 x i32> inreg %rsrc, i32 %val, i32 %voffset, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_i8 |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 |
| ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: BUFFER_STORE_BYTE_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 1 into custom TargetCustom7, addrspace 4) |
| ; CHECK: S_ENDPGM 0 |
| %val.trunc = trunc i32 %val to i8 |
| call void @llvm.amdgcn.raw.buffer.store.i8(i8 %val.trunc, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) |
| ret void |
| } |
| |
| define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_i16(<4 x i32> inreg %rsrc, i32 %val, i32 %voffset, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_i16 |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 |
| ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: BUFFER_STORE_SHORT_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: S_ENDPGM 0 |
| %val.trunc = trunc i32 %val to i16 |
| call void @llvm.amdgcn.raw.buffer.store.i16(i16 %val.trunc, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) |
| ret void |
| } |
| |
| define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16(<4 x i32> inreg %rsrc, half %val, i32 %voffset, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16 |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 |
| ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: BUFFER_STORE_SHORT_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 2 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: S_ENDPGM 0 |
| call void @llvm.amdgcn.raw.buffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) |
| ret void |
| } |
| |
| define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16 |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 |
| ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: S_ENDPGM 0 |
| call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) |
| ret void |
| } |
| |
| define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16(<4 x i32> inreg %rsrc, <4 x half> %val, i32 %voffset, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16 |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 |
| ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 |
| ; CHECK: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 |
| ; CHECK: BUFFER_STORE_DWORDX2_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: S_ENDPGM 0 |
| call void @llvm.amdgcn.raw.buffer.store.v4f16(<4 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) |
| ret void |
| } |
| |
| define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16(<4 x i32> %rsrc, <4 x half> %val, i32 %voffset, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16 |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: successors: %bb.2(0x80000000) |
| ; CHECK: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 |
| ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 |
| ; CHECK: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5 |
| ; CHECK: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6 |
| ; CHECK: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 |
| ; CHECK: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1 |
| ; CHECK: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3 |
| ; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec |
| ; CHECK: bb.2: |
| ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000) |
| ; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub0, implicit $exec |
| ; CHECK: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub1, implicit $exec |
| ; CHECK: [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 |
| ; CHECK: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY8]], implicit $exec |
| ; CHECK: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub0, implicit $exec |
| ; CHECK: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub1, implicit $exec |
| ; CHECK: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1 |
| ; CHECK: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE3]], [[COPY9]], implicit $exec |
| ; CHECK: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc |
| ; CHECK: [[REG_SEQUENCE4:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 |
| ; CHECK: BUFFER_STORE_DWORDX2_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE4]], [[COPY7]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 8 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec |
| ; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc |
| ; CHECK: S_CBRANCH_EXECNZ %bb.2, implicit $exec |
| ; CHECK: bb.3: |
| ; CHECK: successors: %bb.4(0x80000000) |
| ; CHECK: $exec = S_MOV_B64_term [[S_MOV_B64_term]] |
| ; CHECK: bb.4: |
| ; CHECK: S_ENDPGM 0 |
| call void @llvm.amdgcn.raw.buffer.store.v4f16(<4 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) |
| ret void |
| } |
| |
| define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__sgpr_soffset_f32_voffset4095(<4 x i32> inreg %rsrc, float %val, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__sgpr_soffset_f32_voffset4095 |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 |
| ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], $noreg, [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7 + 4095, align 1, addrspace 4) |
| ; CHECK: S_ENDPGM 0 |
| call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 4095, i32 %soffset, i32 0) |
| ret void |
| } |
| |
| define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__sgpr_soffset_f32_voffset4096(<4 x i32> inreg %rsrc, float %val, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__sgpr_soffset_f32_voffset4096 |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 |
| ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec |
| ; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[V_MOV_B32_e32_]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7 + 4096, align 1, addrspace 4) |
| ; CHECK: S_ENDPGM 0 |
| call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 4096, i32 %soffset, i32 0) |
| ret void |
| } |
| |
| define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_16(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_16 |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 |
| ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 |
| ; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] |
| ; CHECK: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec |
| ; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: S_ENDPGM 0 |
| %voffset.add = add i32 %voffset, 16 |
| call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0) |
| ret void |
| } |
| |
| define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_4095(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_4095 |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 |
| ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 |
| ; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] |
| ; CHECK: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec |
| ; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: S_ENDPGM 0 |
| %voffset.add = add i32 %voffset, 4095 |
| call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0) |
| ret void |
| } |
| |
| define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_4096(<4 x i32> inreg %rsrc, float %val, i32 %voffset, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_4096 |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 |
| ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 |
| ; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] |
| ; CHECK: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec |
| ; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: S_ENDPGM 0 |
| %voffset.add = add i32 %voffset, 4096 |
| call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0) |
| ret void |
| } |
| |
| define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4095(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4095 |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 |
| ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 |
| ; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: S_ENDPGM 0 |
| call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 4095, i32 0) |
| ret void |
| } |
| |
| define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4096(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4096 |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 |
| ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 |
| ; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: S_ENDPGM 0 |
| call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 4096, i32 0) |
| ret void |
| } |
| |
| define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_16(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_16 |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 |
| ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 |
| ; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] |
| ; CHECK: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec |
| ; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: S_ENDPGM 0 |
| %voffset.add = add i32 %voffset, 16 |
| call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0) |
| ret void |
| } |
| |
| define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_4095(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_4095 |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 |
| ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 |
| ; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] |
| ; CHECK: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec |
| ; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: S_ENDPGM 0 |
| %voffset.add = add i32 %voffset, 4095 |
| call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0) |
| ret void |
| } |
| |
| define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_4096(<4 x i32> inreg %rsrc, <2 x half> %val, i32 %voffset, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_4096 |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 |
| ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 |
| ; CHECK: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 |
| ; CHECK: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 |
| ; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] |
| ; CHECK: %11:vgpr_32, dead %13:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec |
| ; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: S_ENDPGM 0 |
| %voffset.add = add i32 %voffset, 4096 |
| call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0) |
| ret void |
| } |
| |
| ; An add of the offset is necessary, with a waterfall loop. Make sure the add is done outside of the waterfall loop. |
| define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_offset_add_5000(<4 x i32> %rsrc, float %val, i32 %voffset, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_offset_add_5000 |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: successors: %bb.2(0x80000000) |
| ; CHECK: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 |
| ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 |
| ; CHECK: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 |
| ; CHECK: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5 |
| ; CHECK: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 5000 |
| ; CHECK: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] |
| ; CHECK: %11:vgpr_32, dead %29:sreg_64_xexec = V_ADD_I32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec |
| ; CHECK: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1 |
| ; CHECK: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3 |
| ; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec |
| ; CHECK: bb.2: |
| ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000) |
| ; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub0, implicit $exec |
| ; CHECK: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]].sub1, implicit $exec |
| ; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 |
| ; CHECK: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY8]], implicit $exec |
| ; CHECK: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub0, implicit $exec |
| ; CHECK: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]].sub1, implicit $exec |
| ; CHECK: [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1 |
| ; CHECK: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY9]], implicit $exec |
| ; CHECK: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc |
| ; CHECK: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 |
| ; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], %11, [[REG_SEQUENCE3]], [[COPY6]], 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7, align 1, addrspace 4) |
| ; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec |
| ; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc |
| ; CHECK: S_CBRANCH_EXECNZ %bb.2, implicit $exec |
| ; CHECK: bb.3: |
| ; CHECK: successors: %bb.4(0x80000000) |
| ; CHECK: $exec = S_MOV_B64_term [[S_MOV_B64_term]] |
| ; CHECK: bb.4: |
| ; CHECK: S_ENDPGM 0 |
| %voffset.add = add i32 %voffset, 5000 |
| call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0) |
| ret void |
| } |
| |
| ; An add of the offset is necessary, with a waterfall loop. Make sure the add is done outside of the waterfall loop. |
| define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__5000_voffset__sgpr_soffset_offset(<4 x i32> %rsrc, float %val, i32 inreg %soffset) { |
| ; CHECK-LABEL: name: raw_buffer_store__vgpr_rsrc__vgpr_val__5000_voffset__sgpr_soffset_offset |
| ; CHECK: bb.1 (%ir-block.0): |
| ; CHECK: successors: %bb.2(0x80000000) |
| ; CHECK: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 |
| ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 |
| ; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 |
| ; CHECK: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 |
| ; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 |
| ; CHECK: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2 |
| ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 |
| ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec |
| ; CHECK: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1 |
| ; CHECK: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3 |
| ; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term $exec |
| ; CHECK: bb.2: |
| ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000) |
| ; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub0, implicit $exec |
| ; CHECK: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]].sub1, implicit $exec |
| ; CHECK: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1 |
| ; CHECK: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], [[COPY6]], implicit $exec |
| ; CHECK: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub0, implicit $exec |
| ; CHECK: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]].sub1, implicit $exec |
| ; CHECK: [[REG_SEQUENCE2:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[V_READFIRSTLANE_B32_2]], %subreg.sub0, [[V_READFIRSTLANE_B32_3]], %subreg.sub1 |
| ; CHECK: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE2]], [[COPY7]], implicit $exec |
| ; CHECK: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_1]], [[V_CMP_EQ_U64_e64_]], implicit-def $scc |
| ; CHECK: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 |
| ; CHECK: BUFFER_STORE_DWORD_OFFEN_exact [[COPY4]], [[V_MOV_B32_e32_]], [[REG_SEQUENCE3]], [[COPY5]], 904, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store 4 into custom TargetCustom7 + 5000, align 1, addrspace 4) |
| ; CHECK: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 killed [[S_AND_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec |
| ; CHECK: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def $scc |
| ; CHECK: S_CBRANCH_EXECNZ %bb.2, implicit $exec |
| ; CHECK: bb.3: |
| ; CHECK: successors: %bb.4(0x80000000) |
| ; CHECK: $exec = S_MOV_B64_term [[S_MOV_B64_term]] |
| ; CHECK: bb.4: |
| ; CHECK: S_ENDPGM 0 |
| call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 5000, i32 %soffset, i32 0) |
| ret void |
| } |
| |
| declare void @llvm.amdgcn.raw.buffer.store.i8(i8, <4 x i32>, i32, i32, i32 immarg) |
| declare void @llvm.amdgcn.raw.buffer.store.i16(i16, <4 x i32>, i32, i32, i32 immarg) |
| |
| declare void @llvm.amdgcn.raw.buffer.store.f16(half, <4 x i32>, i32, i32, i32 immarg) |
| declare void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half>, <4 x i32>, i32, i32, i32 immarg) |
| declare void @llvm.amdgcn.raw.buffer.store.v4f16(<4 x half>, <4 x i32>, i32, i32, i32 immarg) |
| |
| declare void @llvm.amdgcn.raw.buffer.store.f32(float, <4 x i32>, i32, i32, i32 immarg) |
| declare void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float>, <4 x i32>, i32, i32, i32 immarg) |
| declare void @llvm.amdgcn.raw.buffer.store.v3f32(<3 x float>, <4 x i32>, i32, i32, i32 immarg) |
| declare void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float>, <4 x i32>, i32, i32, i32 immarg) |
