test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s

---
name: test_sext_s32_to_s64
body: |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_sext_s32_to_s64
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s32)
    ; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
    %0:_(s32) = COPY $vgpr0
    %1:_(s64) = G_SEXT %0
    $vgpr0_vgpr1 = COPY %1
...

---
name: test_sext_s16_to_s64
body: |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_sext_s16_to_s64
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
    ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[TRUNC]](s32)
    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[TRUNC1]](s32)
    ; CHECK: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
    %0:_(s32) = COPY $vgpr0
    %1:_(s16) = G_TRUNC %0
    %2:_(s64) = G_SEXT %1
    $vgpr0_vgpr1 = COPY %2
...

---
name: test_sext_s16_to_s32
body: |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_sext_s16_to_s32
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
    ; CHECK: $vgpr0 = COPY [[ASHR]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s16) = G_TRUNC %0
    %2:_(s32) = G_SEXT %1
    $vgpr0 = COPY %2
...

---
name: test_sext_i1_to_s32
body: |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_sext_i1_to_s32
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
    ; CHECK: $vgpr0 = COPY [[ASHR]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s1) = G_TRUNC %0
    %2:_(s32) = G_SEXT %1
    $vgpr0 = COPY %2
...

---
name: test_sext_v2s16_to_v2s32
body: |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_sext_v2s16_to_v2s32
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
    ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32)
    ; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
    %0:_(<2 x s16>) = COPY $vgpr0
    %1:_(<2 x s32>) = G_SEXT %0
    $vgpr0_vgpr1 = COPY %1
...

---
name: test_sext_v3s16_to_v3s32
body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: test_sext_v3s16_to_v3s32
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
    ; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY]](<4 x s16>), 0
    ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
    ; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0
    ; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>)
    ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
    ; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
    ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
    ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
    ; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32)
    ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
    %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
    %1:_(<3 x s16>) = G_EXTRACT %0, 0
    %2:_(<3 x s32>) = G_SEXT %1
    $vgpr0_vgpr1_vgpr2 = COPY %2
...

---
name: test_sext_v4s16_to_v4s32
body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: test_sext_v4s16_to_v4s32
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
    ; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
    ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
    ; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
    ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
    ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
    ; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
    ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
    ; CHECK: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[C]](s32)
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[ASHR]](s32), [[ASHR1]](s32), [[ASHR2]](s32), [[ASHR3]](s32)
    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
    %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
    %1:_(<4 x s32>) = G_SEXT %0
    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
...

---
name: test_sext_v2s32_to_v2s64
body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: test_sext_v2s32_to_v2s64
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
    ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[UV]](s32)
    ; CHECK: [[SEXT1:%[0-9]+]]:_(s64) = G_SEXT [[UV1]](s32)
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SEXT]](s64), [[SEXT1]](s64)
    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
    %1:_(<2 x s64>) = G_SEXT %0
    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
...

---
name: test_sext_v3s32_to_v3s64
body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2

    ; CHECK-LABEL: name: test_sext_v3s32_to_v3s64
    ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
    ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[UV]](s32)
    ; CHECK: [[SEXT1:%[0-9]+]]:_(s64) = G_SEXT [[UV1]](s32)
    ; CHECK: [[SEXT2:%[0-9]+]]:_(s64) = G_SEXT [[UV2]](s32)
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s64>) = G_BUILD_VECTOR [[SEXT]](s64), [[SEXT1]](s64), [[SEXT2]](s64)
    ; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s64>)
    %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
    %1:_(<3 x s64>) = G_SEXT %0
    S_NOP 0, implicit %1

...

---
name: test_sext_v4s32_to_v4s64
body: |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3

    ; CHECK-LABEL: name: test_sext_v4s32_to_v4s64
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
    ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[UV]](s32)
    ; CHECK: [[SEXT1:%[0-9]+]]:_(s64) = G_SEXT [[UV1]](s32)
    ; CHECK: [[SEXT2:%[0-9]+]]:_(s64) = G_SEXT [[UV2]](s32)
    ; CHECK: [[SEXT3:%[0-9]+]]:_(s64) = G_SEXT [[UV3]](s32)
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[SEXT]](s64), [[SEXT1]](s64), [[SEXT2]](s64), [[SEXT3]](s64)
    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
    %0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    %1:_(<4 x s64>) = G_SEXT %0
    $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %1
...