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//===- IntrinsicsHexagon.td - Defines Hexagon intrinsics ---*- tablegen -*-===//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file defines all of the Hexagon-specific intrinsics.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Definitions for all Hexagon intrinsics.
//
// All Hexagon intrinsics start with "llvm.hexagon.".
let TargetPrefix = "hexagon" in {
/// Hexagon_Intrinsic - Base class for the majority of Hexagon intrinsics.
class Hexagon_Intrinsic<string GCCIntSuffix, list<LLVMType> ret_types,
list<LLVMType> param_types,
list<IntrinsicProperty> properties>
: GCCBuiltin<!strconcat("__builtin_", GCCIntSuffix)>,
Intrinsic<ret_types, param_types, properties>;
/// Hexagon_NonGCC_Intrinsic - Base class for bitcode convertible Hexagon
/// intrinsics.
class Hexagon_NonGCC_Intrinsic<list<LLVMType> ret_types,
list<LLVMType> param_types,
list<IntrinsicProperty> properties>
: Intrinsic<ret_types, param_types, properties>;
}
class Hexagon_mem_memmemsi_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty,
llvm_i32_ty],
[IntrArgMemOnly]>;
class Hexagon_mem_memsisi_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty,
llvm_i32_ty],
[IntrWriteMem]>;
class Hexagon_mem_memdisi_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty,
llvm_i32_ty],
[IntrWriteMem]>;
class Hexagon_mem_memmemsisi_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty,
llvm_i32_ty, llvm_i32_ty],
[IntrArgMemOnly, ImmArg<3>]>;
class Hexagon_mem_memsisisi_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty,
llvm_i32_ty, llvm_i32_ty],
[IntrWriteMem, ImmArg<3>]>;
class Hexagon_mem_memdisisi_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty,
llvm_i32_ty, llvm_i32_ty],
[IntrWriteMem, ImmArg<3>]>;
//
// BUILTIN_INFO_NONCONST(circ_ldd,PTR_ftype_PTRPTRSISI,4)
//
def int_hexagon_circ_ldd :
Hexagon_mem_memmemsisi_Intrinsic<"circ_ldd">;
//
// BUILTIN_INFO_NONCONST(circ_ldw,PTR_ftype_PTRPTRSISI,4)
//
def int_hexagon_circ_ldw :
Hexagon_mem_memmemsisi_Intrinsic<"circ_ldw">;
//
// BUILTIN_INFO_NONCONST(circ_ldh,PTR_ftype_PTRPTRSISI,4)
//
def int_hexagon_circ_ldh :
Hexagon_mem_memmemsisi_Intrinsic<"circ_ldh">;
//
// BUILTIN_INFO_NONCONST(circ_lduh,PTR_ftype_PTRPTRSISI,4)
//
def int_hexagon_circ_lduh :
Hexagon_mem_memmemsisi_Intrinsic<"circ_lduh">;
//
// BUILTIN_INFO_NONCONST(circ_ldb,PTR_ftype_PTRPTRSISI,4)
//
def int_hexagon_circ_ldb :
Hexagon_mem_memmemsisi_Intrinsic<"circ_ldb">;
//
// BUILTIN_INFO_NONCONST(circ_ldub,PTR_ftype_PTRPTRSISI,4)
//
def int_hexagon_circ_ldub :
Hexagon_mem_memmemsisi_Intrinsic<"circ_ldub">;
//
// BUILTIN_INFO_NONCONST(circ_std,PTR_ftype_PTRDISISI,4)
//
def int_hexagon_circ_std :
Hexagon_mem_memdisisi_Intrinsic<"circ_std">;
//
// BUILTIN_INFO_NONCONST(circ_stw,PTR_ftype_PTRSISISI,4)
//
def int_hexagon_circ_stw :
Hexagon_mem_memsisisi_Intrinsic<"circ_stw">;
//
// BUILTIN_INFO_NONCONST(circ_sth,PTR_ftype_PTRSISISI,4)
//
def int_hexagon_circ_sth :
Hexagon_mem_memsisisi_Intrinsic<"circ_sth">;
//
// BUILTIN_INFO_NONCONST(circ_sthhi,PTR_ftype_PTRSISISI,4)
//
def int_hexagon_circ_sthhi :
Hexagon_mem_memsisisi_Intrinsic<"circ_sthhi">;
//
// BUILTIN_INFO_NONCONST(circ_stb,PTR_ftype_PTRSISISI,4)
//
def int_hexagon_circ_stb :
Hexagon_mem_memsisisi_Intrinsic<"circ_stb">;
//
// BUILTIN_INFO(HEXAGON.dcfetch_A,v_ftype_DI*,1)
//
def int_hexagon_prefetch :
Hexagon_Intrinsic<"HEXAGON_prefetch", [], [llvm_ptr_ty], []>;
def int_hexagon_Y2_dccleana :
Hexagon_Intrinsic<"HEXAGON_Y2_dccleana", [], [llvm_ptr_ty], []>;
def int_hexagon_Y2_dccleaninva :
Hexagon_Intrinsic<"HEXAGON_Y2_dccleaninva", [], [llvm_ptr_ty], []>;
def int_hexagon_Y2_dcinva :
Hexagon_Intrinsic<"HEXAGON_Y2_dcinva", [], [llvm_ptr_ty], []>;
def int_hexagon_Y2_dczeroa :
Hexagon_Intrinsic<"HEXAGON_Y2_dczeroa", [], [llvm_ptr_ty],
[IntrWriteMem, IntrArgMemOnly, IntrHasSideEffects]>;
def int_hexagon_Y4_l2fetch :
Hexagon_Intrinsic<"HEXAGON_Y4_l2fetch", [], [llvm_ptr_ty, llvm_i32_ty], []>;
def int_hexagon_Y5_l2fetch :
Hexagon_Intrinsic<"HEXAGON_Y5_l2fetch", [], [llvm_ptr_ty, llvm_i64_ty], []>;
def llvm_ptr32_ty : LLVMPointerType<llvm_i32_ty>;
def llvm_ptr64_ty : LLVMPointerType<llvm_i64_ty>;
// Mark locked loads as read/write to prevent any accidental reordering.
def int_hexagon_L2_loadw_locked :
Hexagon_Intrinsic<"HEXAGON_L2_loadw_locked", [llvm_i32_ty], [llvm_ptr32_ty],
[IntrArgMemOnly, NoCapture<0>]>;
def int_hexagon_L4_loadd_locked :
Hexagon_Intrinsic<"HEXAGON_L4_loadd_locked", [llvm_i64_ty], [llvm_ptr64_ty],
[IntrArgMemOnly, NoCapture<0>]>;
def int_hexagon_S2_storew_locked :
Hexagon_Intrinsic<"HEXAGON_S2_storew_locked", [llvm_i32_ty],
[llvm_ptr32_ty, llvm_i32_ty], [IntrArgMemOnly, NoCapture<0>]>;
def int_hexagon_S4_stored_locked :
Hexagon_Intrinsic<"HEXAGON_S4_stored_locked", [llvm_i32_ty],
[llvm_ptr64_ty, llvm_i64_ty], [IntrArgMemOnly, NoCapture<0>]>;
def int_hexagon_vmemcpy : Hexagon_Intrinsic<"hexagon_vmemcpy",
[], [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty],
[IntrArgMemOnly, NoCapture<0>, NoCapture<1>, WriteOnly<0>, ReadOnly<1>]>;
def int_hexagon_vmemset : Hexagon_Intrinsic<"hexagon_vmemset",
[], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
[IntrArgMemOnly, NoCapture<0>, WriteOnly<0>]>;
multiclass Hexagon_custom_circ_ld_Intrinsic<LLVMType ElTy> {
def NAME#_pci : Hexagon_NonGCC_Intrinsic<
[ElTy, llvm_ptr_ty],
[llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty],
[IntrArgMemOnly, NoCapture<3>]>;
def NAME#_pcr : Hexagon_NonGCC_Intrinsic<
[ElTy, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_ptr_ty],
[IntrArgMemOnly, NoCapture<2>]>;
}
defm int_hexagon_L2_loadrub : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
defm int_hexagon_L2_loadrb : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
defm int_hexagon_L2_loadruh : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
defm int_hexagon_L2_loadrh : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
defm int_hexagon_L2_loadri : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>;
defm int_hexagon_L2_loadrd : Hexagon_custom_circ_ld_Intrinsic<llvm_i64_ty>;
multiclass Hexagon_custom_circ_st_Intrinsic<LLVMType ElTy> {
def NAME#_pci : Hexagon_NonGCC_Intrinsic<
[llvm_ptr_ty],
[llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, ElTy, llvm_ptr_ty],
[IntrArgMemOnly, NoCapture<4>]>;
def NAME#_pcr : Hexagon_NonGCC_Intrinsic<
[llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, ElTy, llvm_ptr_ty],
[IntrArgMemOnly, NoCapture<3>]>;
}
defm int_hexagon_S2_storerb : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>;
defm int_hexagon_S2_storerh : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>;
defm int_hexagon_S2_storerf : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>;
defm int_hexagon_S2_storeri : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>;
defm int_hexagon_S2_storerd : Hexagon_custom_circ_st_Intrinsic<llvm_i64_ty>;
// The front-end emits the intrinsic call with only two arguments. The third
// argument from the builtin is already used by front-end to write to memory
// by generating a store.
class Hexagon_custom_brev_ld_Intrinsic<LLVMType ElTy>
: Hexagon_NonGCC_Intrinsic<
[ElTy, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty],
[IntrReadMem]>;
def int_hexagon_L2_loadrub_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
def int_hexagon_L2_loadrb_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
def int_hexagon_L2_loadruh_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
def int_hexagon_L2_loadrh_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
def int_hexagon_L2_loadri_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>;
def int_hexagon_L2_loadrd_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i64_ty>;
def int_hexagon_S2_storerb_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_stb">;
def int_hexagon_S2_storerh_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_sth">;
def int_hexagon_S2_storerf_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_sthhi">;
def int_hexagon_S2_storeri_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_stw">;
def int_hexagon_S2_storerd_pbr : Hexagon_mem_memdisi_Intrinsic<"brev_std">;
//
// Masked vector stores
//
//
// Hexagon_vv64ivmemv512_Intrinsic<string GCCIntSuffix>
// tag: V6_vS32b_qpred_ai
class Hexagon_vv64ivmemv512_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[], [llvm_v512i1_ty,llvm_ptr_ty,llvm_v16i32_ty],
[IntrArgMemOnly]>;
//
// Hexagon_vv128ivmemv1024_Intrinsic<string GCCIntSuffix>
// tag: V6_vS32b_qpred_ai_128B
class Hexagon_vv128ivmemv1024_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[], [llvm_v1024i1_ty,llvm_ptr_ty,llvm_v32i32_ty],
[IntrArgMemOnly]>;
def int_hexagon_V6_vS32b_qpred_ai :
Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai">;
def int_hexagon_V6_vS32b_nqpred_ai :
Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai">;
def int_hexagon_V6_vS32b_nt_qpred_ai :
Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai">;
def int_hexagon_V6_vS32b_nt_nqpred_ai :
Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai">;
def int_hexagon_V6_vS32b_qpred_ai_128B :
Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai_128B">;
def int_hexagon_V6_vS32b_nqpred_ai_128B :
Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai_128B">;
def int_hexagon_V6_vS32b_nt_qpred_ai_128B :
Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai_128B">;
def int_hexagon_V6_vS32b_nt_nqpred_ai_128B :
Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai_128B">;
def int_hexagon_V6_vmaskedstoreq :
Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstoreq">;
def int_hexagon_V6_vmaskedstorenq :
Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstorenq">;
def int_hexagon_V6_vmaskedstorentq :
Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstorentq">;
def int_hexagon_V6_vmaskedstorentnq :
Hexagon_vv64ivmemv512_Intrinsic<"HEXAGON_V6_vmaskedstorentnq">;
def int_hexagon_V6_vmaskedstoreq_128B :
Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstoreq_128B">;
def int_hexagon_V6_vmaskedstorenq_128B :
Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorenq_128B">;
def int_hexagon_V6_vmaskedstorentq_128B :
Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorentq_128B">;
def int_hexagon_V6_vmaskedstorentnq_128B :
Hexagon_vv128ivmemv1024_Intrinsic<"HEXAGON_V6_vmaskedstorentnq_128B">;
class Hexagon_V65_vvmemiiv512_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,
llvm_v16i32_ty],
[IntrArgMemOnly]>;
class Hexagon_V65_vvmemiiv1024_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,
llvm_v32i32_ty],
[IntrArgMemOnly]>;
class Hexagon_V65_vvmemiiv2048_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,
llvm_v64i32_ty],
[IntrArgMemOnly]>;
class Hexagon_V65_vvmemv64iiiv512_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[], [llvm_ptr_ty,llvm_v512i1_ty,llvm_i32_ty,
llvm_i32_ty,llvm_v16i32_ty],
[IntrArgMemOnly]>;
class Hexagon_V65_vvmemv128iiiv1024_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[], [llvm_ptr_ty,llvm_v1024i1_ty,llvm_i32_ty,
llvm_i32_ty,llvm_v32i32_ty],
[IntrArgMemOnly]>;
class Hexagon_V65_vvmemv64iiiv1024_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[], [llvm_ptr_ty,llvm_v512i1_ty,llvm_i32_ty,
llvm_i32_ty,llvm_v32i32_ty],
[IntrArgMemOnly]>;
class Hexagon_V65_vvmemv128iiiv2048_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[], [llvm_ptr_ty,llvm_v1024i1_ty,llvm_i32_ty,
llvm_i32_ty,llvm_v64i32_ty],
[IntrArgMemOnly]>;
def int_hexagon_V6_vgathermw :
Hexagon_V65_vvmemiiv512_Intrinsic<"HEXAGON_V6_vgathermw">;
def int_hexagon_V6_vgathermw_128B :
Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermw_128B">;
def int_hexagon_V6_vgathermh :
Hexagon_V65_vvmemiiv512_Intrinsic<"HEXAGON_V6_vgathermh">;
def int_hexagon_V6_vgathermh_128B :
Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermh_128B">;
def int_hexagon_V6_vgathermhw :
Hexagon_V65_vvmemiiv1024_Intrinsic<"HEXAGON_V6_vgathermhw">;
def int_hexagon_V6_vgathermhw_128B :
Hexagon_V65_vvmemiiv2048_Intrinsic<"HEXAGON_V6_vgathermhw_128B">;
def int_hexagon_V6_vgathermwq :
Hexagon_V65_vvmemv64iiiv512_Intrinsic<"HEXAGON_V6_vgathermwq">;
def int_hexagon_V6_vgathermwq_128B :
Hexagon_V65_vvmemv128iiiv1024_Intrinsic<"HEXAGON_V6_vgathermwq_128B">;
def int_hexagon_V6_vgathermhq :
Hexagon_V65_vvmemv64iiiv512_Intrinsic<"HEXAGON_V6_vgathermhq">;
def int_hexagon_V6_vgathermhq_128B :
Hexagon_V65_vvmemv128iiiv1024_Intrinsic<"HEXAGON_V6_vgathermhq_128B">;
def int_hexagon_V6_vgathermhwq :
Hexagon_V65_vvmemv64iiiv1024_Intrinsic<"HEXAGON_V6_vgathermhwq">;
def int_hexagon_V6_vgathermhwq_128B :
Hexagon_V65_vvmemv128iiiv2048_Intrinsic<"HEXAGON_V6_vgathermhwq_128B">;
class Hexagon_V65_viiv512v512_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[], [llvm_i32_ty,llvm_i32_ty,
llvm_v16i32_ty,llvm_v16i32_ty],
[IntrWriteMem]>;
class Hexagon_V65_viiv1024v1024_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[], [llvm_i32_ty,llvm_i32_ty,
llvm_v32i32_ty,llvm_v32i32_ty],
[IntrWriteMem]>;
class Hexagon_V65_vv64iiiv512v512_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[], [llvm_v512i1_ty,llvm_i32_ty,
llvm_i32_ty,llvm_v16i32_ty,
llvm_v16i32_ty],
[IntrWriteMem]>;
class Hexagon_V65_vv128iiiv1024v1024_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[], [llvm_v1024i1_ty,llvm_i32_ty,
llvm_i32_ty,llvm_v32i32_ty,
llvm_v32i32_ty],
[IntrWriteMem]>;
class Hexagon_V65_viiv1024v512_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[], [llvm_i32_ty,llvm_i32_ty,
llvm_v32i32_ty,llvm_v16i32_ty],
[IntrWriteMem]>;
class Hexagon_V65_viiv2048v1024_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[], [llvm_i32_ty,llvm_i32_ty,
llvm_v64i32_ty,llvm_v32i32_ty],
[IntrWriteMem]>;
class Hexagon_V65_vv64iiiv1024v512_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[], [llvm_v512i1_ty,llvm_i32_ty,
llvm_i32_ty,llvm_v32i32_ty,
llvm_v16i32_ty],
[IntrWriteMem]>;
class Hexagon_V65_vv128iiiv2048v1024_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[], [llvm_v1024i1_ty,llvm_i32_ty,
llvm_i32_ty,llvm_v64i32_ty,
llvm_v32i32_ty],
[IntrWriteMem]>;
class Hexagon_V65_v2048_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v64i32_ty], [],
[IntrNoMem]>;
//
// BUILTIN_INFO(HEXAGON.V6_vscattermw,v_ftype_SISIVIVI,4)
// tag : V6_vscattermw
def int_hexagon_V6_vscattermw :
Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermw">;
//
// BUILTIN_INFO(HEXAGON.V6_vscattermw_128B,v_ftype_SISIVIVI,4)
// tag : V6_vscattermw_128B
def int_hexagon_V6_vscattermw_128B :
Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermw_128B">;
//
// BUILTIN_INFO(HEXAGON.V6_vscattermh,v_ftype_SISIVIVI,4)
// tag : V6_vscattermh
def int_hexagon_V6_vscattermh :
Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermh">;
//
// BUILTIN_INFO(HEXAGON.V6_vscattermh_128B,v_ftype_SISIVIVI,4)
// tag : V6_vscattermh_128B
def int_hexagon_V6_vscattermh_128B :
Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermh_128B">;
//
// BUILTIN_INFO(HEXAGON.V6_vscattermw_add,v_ftype_SISIVIVI,4)
// tag : V6_vscattermw_add
def int_hexagon_V6_vscattermw_add :
Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermw_add">;
//
// BUILTIN_INFO(HEXAGON.V6_vscattermw_add_128B,v_ftype_SISIVIVI,4)
// tag : V6_vscattermw_add_128B
def int_hexagon_V6_vscattermw_add_128B :
Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermw_add_128B">;
//
// BUILTIN_INFO(HEXAGON.V6_vscattermh_add,v_ftype_SISIVIVI,4)
// tag : V6_vscattermh_add
def int_hexagon_V6_vscattermh_add :
Hexagon_V65_viiv512v512_Intrinsic<"HEXAGON_V6_vscattermh_add">;
//
// BUILTIN_INFO(HEXAGON.V6_vscattermh_add_128B,v_ftype_SISIVIVI,4)
// tag : V6_vscattermh_add_128B
def int_hexagon_V6_vscattermh_add_128B :
Hexagon_V65_viiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermh_add_128B">;
//
// BUILTIN_INFO(HEXAGON.V6_vscattermwq,v_ftype_QVSISIVIVI,5)
// tag : V6_vscattermwq
def int_hexagon_V6_vscattermwq :
Hexagon_V65_vv64iiiv512v512_Intrinsic<"HEXAGON_V6_vscattermwq">;
//
// BUILTIN_INFO(HEXAGON.V6_vscattermwq_128B,v_ftype_QVSISIVIVI,5)
// tag : V6_vscattermwq_128B
def int_hexagon_V6_vscattermwq_128B :
Hexagon_V65_vv128iiiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermwq_128B">;
//
// BUILTIN_INFO(HEXAGON.V6_vscattermhq,v_ftype_QVSISIVIVI,5)
// tag : V6_vscattermhq
def int_hexagon_V6_vscattermhq :
Hexagon_V65_vv64iiiv512v512_Intrinsic<"HEXAGON_V6_vscattermhq">;
//
// BUILTIN_INFO(HEXAGON.V6_vscattermhq_128B,v_ftype_QVSISIVIVI,5)
// tag : V6_vscattermhq_128B
def int_hexagon_V6_vscattermhq_128B :
Hexagon_V65_vv128iiiv1024v1024_Intrinsic<"HEXAGON_V6_vscattermhq_128B">;
//
// BUILTIN_INFO(HEXAGON.V6_vscattermhw,v_ftype_SISIVDVI,4)
// tag : V6_vscattermhw
def int_hexagon_V6_vscattermhw :
Hexagon_V65_viiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhw">;
//
// BUILTIN_INFO(HEXAGON.V6_vscattermhw_128B,v_ftype_SISIVDVI,4)
// tag : V6_vscattermhw_128B
def int_hexagon_V6_vscattermhw_128B :
Hexagon_V65_viiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhw_128B">;
//
// BUILTIN_INFO(HEXAGON.V6_vscattermhwq,v_ftype_QVSISIVDVI,5)
// tag : V6_vscattermhwq
def int_hexagon_V6_vscattermhwq :
Hexagon_V65_vv64iiiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhwq">;
//
// BUILTIN_INFO(HEXAGON.V6_vscattermhwq_128B,v_ftype_QVSISIVDVI,5)
// tag : V6_vscattermhwq_128B
def int_hexagon_V6_vscattermhwq_128B :
Hexagon_V65_vv128iiiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhwq_128B">;
//
// BUILTIN_INFO(HEXAGON.V6_vscattermhw_add,v_ftype_SISIVDVI,4)
// tag : V6_vscattermhw_add
def int_hexagon_V6_vscattermhw_add :
Hexagon_V65_viiv1024v512_Intrinsic<"HEXAGON_V6_vscattermhw_add">;
//
// BUILTIN_INFO(HEXAGON.V6_vscattermhw_add_128B,v_ftype_SISIVDVI,4)
// tag : V6_vscattermhw_add_128B
def int_hexagon_V6_vscattermhw_add_128B :
Hexagon_V65_viiv2048v1024_Intrinsic<"HEXAGON_V6_vscattermhw_add_128B">;
// Auto-generated intrinsics
// tag : S2_vsatwh
class Hexagon_i32_i64_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i32_ty], [llvm_i64_ty],
[IntrNoMem]>;
// tag : V6_vrmpybusv
class Hexagon_v16i32_v16i32v16i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
[IntrNoMem]>;
// tag : V6_vrmpybusv
class Hexagon_v32i32_v32i32v32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
[IntrNoMem]>;
// tag : V6_vaslw_acc
class Hexagon_v16i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix,
list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
!listconcat([IntrNoMem], intr_properties)>;
// tag : V6_vaslw_acc
class Hexagon_v32i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix,
list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
!listconcat([IntrNoMem], intr_properties)>;
// tag : V6_vmux
class Hexagon_v16i32_v512i1v16i32v16i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v16i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty],
[IntrNoMem]>;
// tag : V6_vmux
class Hexagon_v32i32_v1024i1v32i32v32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty],
[IntrNoMem]>;
// tag : S2_tableidxd_goodsyntax
class Hexagon_i32_i32i32i32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],
[IntrNoMem, ImmArg<2>, ImmArg<3>]>;
// tag : V6_vandnqrt_acc
class Hexagon_v16i32_v16i32v512i1i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v512i1_ty,llvm_i32_ty],
[IntrNoMem]>;
// tag : V6_vandnqrt_acc
class Hexagon_v32i32_v32i32v1024i1i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v1024i1_ty,llvm_i32_ty],
[IntrNoMem]>;
// tag : V6_vrmpybusi
class Hexagon_v32i32_v32i32i32i32_Intrinsic<string GCCIntSuffix,
list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty],
!listconcat([IntrNoMem], intr_properties)>;
// tag : V6_vrmpybusi
class Hexagon_v64i32_v64i32i32i32_Intrinsic<string GCCIntSuffix,
list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty],
!listconcat([IntrNoMem], intr_properties)>;
// tag : V6_vsubb_dv
class Hexagon_v64i32_v64i32v64i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty],
!listconcat([IntrNoMem], intr_properties)>;
// tag : M2_mpysu_up
class Hexagon_i32_i32i32_Intrinsic<string GCCIntSuffix,
list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty],
!listconcat([IntrNoMem], intr_properties)>;
// tag : M2_mpyud_acc_ll_s0
class Hexagon_i64_i64i32i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty,llvm_i32_ty],
!listconcat([IntrNoMem], intr_properties)>;
// tag : S2_lsr_i_r_nac
class Hexagon_i32_i32i32i32_Intrinsic<string GCCIntSuffix,
list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],
!listconcat([IntrNoMem], intr_properties)>;
// tag : M2_cmpysc_s0
class Hexagon_i64_i32i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i64_ty], [llvm_i32_ty,llvm_i32_ty],
!listconcat([IntrNoMem], intr_properties)>;
// tag : V6_lo
class Hexagon_v16i32_v32i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v16i32_ty], [llvm_v32i32_ty],
!listconcat([IntrNoMem], intr_properties)>;
// tag : V6_lo
class Hexagon_v32i32_v64i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v64i32_ty],
!listconcat([IntrNoMem], intr_properties)>;
// tag : S2_shuffoh
class Hexagon_i64_i64i64_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty],
[IntrNoMem]>;
// tag : F2_sfmax
class Hexagon_float_floatfloat_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_float_ty], [llvm_float_ty,llvm_float_ty],
[IntrNoMem, Throws]>;
// tag : A2_vabswsat
class Hexagon_i64_i64_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i64_ty], [llvm_i64_ty],
[IntrNoMem]>;
// tag :
class Hexagon_v32i32_v32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v32i32_ty],
[IntrNoMem]>;
// tag : V6_ldnp0
class Hexagon_v16i32_i32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v16i32_ty], [llvm_i32_ty,llvm_i32_ty],
[IntrNoMem]>;
// tag : V6_ldnp0
class Hexagon_v32i32_i32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_i32_ty,llvm_i32_ty],
[IntrNoMem]>;
// tag : V6_vdmpyhb
class Hexagon_v16i32_v16i32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i32_ty],
[IntrNoMem]>;
// tag : V6_vdmpyhb
class Hexagon_v32i32_v32i32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
[IntrNoMem]>;
// tag : A4_vcmphgti
class Hexagon_i32_i64i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i32_ty], [llvm_i64_ty,llvm_i32_ty],
!listconcat([IntrNoMem], intr_properties)>;
// tag :
class Hexagon_v32i32_v16i32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i32_ty],
[IntrNoMem]>;
// tag : S6_rol_i_p_or
class Hexagon_i64_i64i64i32_Intrinsic<string GCCIntSuffix,
list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty],
!listconcat([IntrNoMem], intr_properties)>;
// tag : V6_vgtuh_and
class Hexagon_v512i1_v512i1v16i32v16i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty],
[IntrNoMem]>;
// tag : V6_vgtuh_and
class Hexagon_v1024i1_v1024i1v32i32v32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty],
[IntrNoMem]>;
// tag : A2_abssat
class Hexagon_i32_i32_Intrinsic<string GCCIntSuffix,
list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i32_ty], [llvm_i32_ty],
!listconcat([IntrNoMem], intr_properties)>;
// tag : A2_vcmpwgtu
class Hexagon_i32_i64i64_Intrinsic<string GCCIntSuffix,
list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty],
!listconcat([IntrNoMem], intr_properties)>;
// tag : V6_vtmpybus_acc
class Hexagon_v64i32_v64i32v64i32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty],
[IntrNoMem]>;
// tag : F2_conv_df2uw_chop
class Hexagon_i32_double_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i32_ty], [llvm_double_ty],
[IntrNoMem]>;
// tag : V6_pred_or
class Hexagon_v512i1_v512i1v512i1_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v512i1_ty],
[IntrNoMem]>;
// tag : V6_pred_or
class Hexagon_v1024i1_v1024i1v1024i1_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v1024i1_ty],
[IntrNoMem]>;
// tag : S2_asr_i_p_rnd_goodsyntax
class Hexagon_i64_i64i32_Intrinsic<string GCCIntSuffix,
list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty],
!listconcat([IntrNoMem], intr_properties)>;
// tag : F2_conv_w2df
class Hexagon_double_i32_Intrinsic<string GCCIntSuffix,
list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_double_ty], [llvm_i32_ty],
!listconcat([IntrNoMem], intr_properties)>;
// tag : V6_vunpackuh
class Hexagon_v32i32_v16i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v16i32_ty],
[IntrNoMem]>;
// tag : V6_vunpackuh
class Hexagon_v64i32_v32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v64i32_ty], [llvm_v32i32_ty],
[IntrNoMem]>;
// tag : V6_vadduhw_acc
class Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty],
[IntrNoMem]>;
// tag : V6_vadduhw_acc
class Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty],
[IntrNoMem]>;
// tag : M2_vdmacs_s0
class Hexagon_i64_i64i64i64_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i64_ty],
[IntrNoMem]>;
// tag : V6_vrmpybub_rtt_acc
class Hexagon_v32i32_v32i32v16i32i64_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i64_ty],
[IntrNoMem]>;
// tag : V6_vrmpybub_rtt_acc
class Hexagon_v64i32_v64i32v32i32i64_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i64_ty],
[IntrNoMem]>;
// tag : V6_ldu0
class Hexagon_v16i32_i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v16i32_ty], [llvm_i32_ty],
[IntrNoMem]>;
// tag : V6_ldu0
class Hexagon_v32i32_i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_i32_ty],
[IntrNoMem]>;
// tag : S4_extract_rp
class Hexagon_i32_i32i64_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i32_ty], [llvm_i32_ty,llvm_i64_ty],
[IntrNoMem]>;
// tag : V6_vdmpyhsuisat
class Hexagon_v16i32_v32i32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v16i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
[IntrNoMem]>;
// tag : V6_vdmpyhsuisat
class Hexagon_v32i32_v64i32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v64i32_ty,llvm_i32_ty],
[IntrNoMem]>;
// tag : A2_addsp
class Hexagon_i64_i32i64_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i64_ty], [llvm_i32_ty,llvm_i64_ty],
[IntrNoMem]>;
// tag : V6_extractw
class Hexagon_i32_v16i32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i32_ty], [llvm_v16i32_ty,llvm_i32_ty],
[IntrNoMem]>;
// tag : V6_extractw
class Hexagon_i32_v32i32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
[IntrNoMem]>;
// tag : V6_vlutvwhi
class Hexagon_v32i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix,
list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
!listconcat([IntrNoMem], intr_properties)>;
// tag : V6_vlutvwhi
class Hexagon_v64i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix,
list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
!listconcat([IntrNoMem], intr_properties)>;
// tag : V6_vgtuh
class Hexagon_v512i1_v16i32v16i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v512i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
[IntrNoMem]>;
// tag : V6_vgtuh
class Hexagon_v1024i1_v32i32v32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
[IntrNoMem]>;
// tag : F2_sffma_lib
class Hexagon_float_floatfloatfloat_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_float_ty], [llvm_float_ty,llvm_float_ty,llvm_float_ty],
[IntrNoMem, Throws]>;
// tag : F2_conv_ud2df
class Hexagon_double_i64_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_double_ty], [llvm_i64_ty],
[IntrNoMem]>;
// tag : S2_vzxthw
class Hexagon_i64_i32_Intrinsic<string GCCIntSuffix,
list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i64_ty], [llvm_i32_ty],
!listconcat([IntrNoMem], intr_properties)>;
// tag : V6_vtmpyhb
class Hexagon_v64i32_v64i32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty],
[IntrNoMem]>;
// tag : V6_vshufoeh
class Hexagon_v32i32_v16i32v16i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty],
[IntrNoMem]>;
// tag : V6_vshufoeh
class Hexagon_v64i32_v32i32v32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty],
[IntrNoMem]>;
// tag : V6_vlut4
class Hexagon_v16i32_v16i32i64_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i64_ty],
[IntrNoMem]>;
// tag : V6_vlut4
class Hexagon_v32i32_v32i32i64_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i64_ty],
[IntrNoMem]>;
// tag :
class Hexagon_v16i32_v16i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v16i32_ty], [llvm_v16i32_ty],
[IntrNoMem]>;
// tag : F2_conv_uw2sf
class Hexagon_float_i32_Intrinsic<string GCCIntSuffix,
list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_float_ty], [llvm_i32_ty],
!listconcat([IntrNoMem], intr_properties)>;
// tag : V6_vswap
class Hexagon_v32i32_v512i1v16i32v16i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_v16i32_ty],
[IntrNoMem]>;
// tag : V6_vswap
class Hexagon_v64i32_v1024i1v32i32v32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v64i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_v32i32_ty],
[IntrNoMem]>;
// tag : V6_vandnqrt
class Hexagon_v16i32_v512i1i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v16i32_ty], [llvm_v512i1_ty,llvm_i32_ty],
[IntrNoMem]>;
// tag : V6_vandnqrt
class Hexagon_v32i32_v1024i1i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_i32_ty],
[IntrNoMem]>;
// tag : V6_vmpyub
class Hexagon_v64i32_v32i32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i32_ty],
[IntrNoMem]>;
// tag : A5_ACS
class Hexagon_i64i32_i64i64i64_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i64_ty,llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i64_ty],
[IntrNoMem]>;
// tag : V6_vunpackob
class Hexagon_v32i32_v32i32v16i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty],
[IntrNoMem]>;
// tag : V6_vunpackob
class Hexagon_v64i32_v64i32v32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty],
[IntrNoMem]>;
// tag : V6_vmpyhsat_acc
class Hexagon_v32i32_v32i32v16i32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i32_ty],
[IntrNoMem]>;
// tag : V6_vmpyhsat_acc
class Hexagon_v64i32_v64i32v32i32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i32_ty],
[IntrNoMem]>;
// tag : V6_vaddcarrysat
class Hexagon_v16i32_v16i32v16i32v512i1_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v512i1_ty],
[IntrNoMem]>;
// tag : V6_vaddcarrysat
class Hexagon_v32i32_v32i32v32i32v1024i1_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v1024i1_ty],
[IntrNoMem]>;
// tag : V6_vlutvvb_oracc
class Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<string GCCIntSuffix,
list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
!listconcat([IntrNoMem], intr_properties)>;
// tag : V6_vlutvvb_oracc
class Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<string GCCIntSuffix, list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
!listconcat([IntrNoMem], intr_properties)>;
// tag : V6_vrmpybub_rtt
class Hexagon_v32i32_v16i32i64_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i64_ty],
[IntrNoMem]>;
// tag : V6_vrmpybub_rtt
class Hexagon_v64i32_v32i32i64_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i64_ty],
[IntrNoMem]>;
// tag : A4_addp_c
class Hexagon_i64i32_i64i64i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i64_ty,llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty],
[IntrNoMem]>;
// tag : V6_vrsadubi_acc
class Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<string GCCIntSuffix,
list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty],
!listconcat([IntrNoMem], intr_properties)>;
// tag : V6_vrsadubi_acc
class Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<string GCCIntSuffix,
list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty],
!listconcat([IntrNoMem], intr_properties)>;
// tag : F2_conv_df2sf
class Hexagon_float_double_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_float_ty], [llvm_double_ty],
[IntrNoMem]>;
// tag : V6_vandvqv
class Hexagon_v16i32_v512i1v16i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v16i32_ty], [llvm_v512i1_ty,llvm_v16i32_ty],
[IntrNoMem]>;
// tag : V6_vandvqv
class Hexagon_v32i32_v1024i1v32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v1024i1_ty,llvm_v32i32_ty],
[IntrNoMem]>;
// tag : C2_vmux
class Hexagon_i64_i32i64i64_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i64_ty], [llvm_i32_ty,llvm_i64_ty,llvm_i64_ty],
[IntrNoMem]>;
// tag : F2_sfcmpeq
class Hexagon_i32_floatfloat_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i32_ty], [llvm_float_ty,llvm_float_ty],
[IntrNoMem, Throws]>;
// tag : V6_vmpahhsat
class Hexagon_v16i32_v16i32v16i32i64_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i64_ty],
[IntrNoMem]>;
// tag : V6_vmpahhsat
class Hexagon_v32i32_v32i32v32i32i64_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i64_ty],
[IntrNoMem]>;
// tag : V6_vandvrt
class Hexagon_v512i1_v16i32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v512i1_ty], [llvm_v16i32_ty,llvm_i32_ty],
[IntrNoMem]>;
// tag : V6_vandvrt
class Hexagon_v1024i1_v32i32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_i32_ty],
[IntrNoMem]>;
// tag : V6_vsubcarry
class Hexagon_custom_v16i32v512i1_v16i32v16i32v512i1_Intrinsic
: Hexagon_NonGCC_Intrinsic<
[llvm_v16i32_ty,llvm_v512i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v512i1_ty],
[IntrNoMem]>;
// tag : V6_vsubcarry
class Hexagon_custom_v32i32v1024i1_v32i32v32i32v1024i1_Intrinsic_128B
: Hexagon_NonGCC_Intrinsic<
[llvm_v32i32_ty,llvm_v1024i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v1024i1_ty],
[IntrNoMem]>;
// tag : F2_sffixupr
class Hexagon_float_float_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_float_ty], [llvm_float_ty],
[IntrNoMem, Throws]>;
// tag : V6_vandvrt_acc
class Hexagon_v512i1_v512i1v16i32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v512i1_ty], [llvm_v512i1_ty,llvm_v16i32_ty,llvm_i32_ty],
[IntrNoMem]>;
// tag : V6_vandvrt_acc
class Hexagon_v1024i1_v1024i1v32i32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v1024i1_ty], [llvm_v1024i1_ty,llvm_v32i32_ty,llvm_i32_ty],
[IntrNoMem]>;
// tag : F2_dfsub
class Hexagon_double_doubledouble_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_double_ty], [llvm_double_ty,llvm_double_ty],
[IntrNoMem, Throws]>;
// tag : V6_vmpyowh_sacc
class Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty],
[IntrNoMem]>;
// tag : V6_vmpyowh_sacc
class Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty],
[IntrNoMem]>;
// tag : S2_insertp
class Hexagon_i64_i64i64i32i32_Intrinsic<string GCCIntSuffix,
list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty,llvm_i32_ty],
!listconcat([IntrNoMem], intr_properties)>;
// tag : F2_sfinvsqrta
class Hexagon_floati32_float_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_float_ty,llvm_i32_ty], [llvm_float_ty],
[IntrNoMem, Throws]>;
// tag : V6_vtran2x2_map
class Hexagon_v16i32v16i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v16i32_ty,llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
[IntrNoMem]>;
// tag : V6_vtran2x2_map
class Hexagon_v32i32v32i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty,llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
[IntrNoMem]>;
// tag : V6_vlutvwh_oracc
class Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<string GCCIntSuffix,
list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty],
!listconcat([IntrNoMem], intr_properties)>;
// tag : V6_vlutvwh_oracc
class Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<string GCCIntSuffix,
list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty],
!listconcat([IntrNoMem], intr_properties)>;
// tag : F2_dfcmpge
class Hexagon_i32_doubledouble_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i32_ty], [llvm_double_ty,llvm_double_ty],
[IntrNoMem, Throws]>;
// tag : F2_conv_df2d_chop
class Hexagon_i64_double_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i64_ty], [llvm_double_ty],
[IntrNoMem]>;
// tag : F2_conv_sf2w
class Hexagon_i32_float_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i32_ty], [llvm_float_ty],
[IntrNoMem]>;
// tag : F2_sfclass
class Hexagon_i32_floati32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i32_ty], [llvm_float_ty,llvm_i32_ty],
[IntrNoMem, Throws, ImmArg<1>]>;
// tag : F2_conv_sf2ud_chop
class Hexagon_i64_float_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i64_ty], [llvm_float_ty],
[IntrNoMem]>;
// tag : V6_pred_scalar2v2
class Hexagon_v512i1_i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v512i1_ty], [llvm_i32_ty],
[IntrNoMem]>;
// tag : V6_pred_scalar2v2
class Hexagon_v1024i1_i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v1024i1_ty], [llvm_i32_ty],
[IntrNoMem]>;
// tag : F2_sfrecipa
class Hexagon_floati32_floatfloat_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_float_ty,llvm_i32_ty], [llvm_float_ty,llvm_float_ty],
[IntrNoMem, Throws]>;
// tag : V6_vprefixqh
class Hexagon_v16i32_v512i1_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v16i32_ty], [llvm_v512i1_ty],
[IntrNoMem]>;
// tag : V6_vprefixqh
class Hexagon_v32i32_v1024i1_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v1024i1_ty],
[IntrNoMem]>;
// tag : V6_vdmpyhisat_acc
class Hexagon_v16i32_v16i32v32i32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v32i32_ty,llvm_i32_ty],
[IntrNoMem]>;
// tag : V6_vdmpyhisat_acc
class Hexagon_v32i32_v32i32v64i32i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v64i32_ty,llvm_i32_ty],
[IntrNoMem]>;
// tag : F2_conv_ud2sf
class Hexagon_float_i64_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_float_ty], [llvm_i64_ty],
[IntrNoMem]>;
// tag : F2_conv_sf2df
class Hexagon_double_float_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_double_ty], [llvm_float_ty],
[IntrNoMem]>;
// tag : F2_sffma_sc
class Hexagon_float_floatfloatfloati32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_float_ty], [llvm_float_ty,llvm_float_ty,llvm_float_ty,llvm_i32_ty],
[IntrNoMem, Throws]>;
// tag : F2_dfclass
class Hexagon_i32_doublei32_Intrinsic<string GCCIntSuffix,
list<IntrinsicProperty> intr_properties = []>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i32_ty], [llvm_double_ty,llvm_i32_ty],
!listconcat([IntrNoMem, Throws], intr_properties)>;
// tag : V6_vd0
class Hexagon_v16i32__Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v16i32_ty], [],
[IntrNoMem]>;
// tag : V6_vd0
class Hexagon_v32i32__Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v32i32_ty], [],
[IntrNoMem]>;
// tag : V6_vdd0
class Hexagon_v64i32__Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v64i32_ty], [],
[IntrNoMem]>;
// tag : S2_insert_rp
class Hexagon_i32_i32i32i64_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i64_ty],
[IntrNoMem]>;
// tag : V6_vassignp
class Hexagon_v64i32_v64i32_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v64i32_ty], [llvm_v64i32_ty],
[IntrNoMem]>;
// tag : A6_vminub_RdP
class Hexagon_i64i32_i64i64_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_i64_ty,llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty],
[IntrNoMem]>;
// tag : V6_pred_not
class Hexagon_v512i1_v512i1_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v512i1_ty], [llvm_v512i1_ty],
[IntrNoMem]>;
// tag : V6_pred_not
class Hexagon_v1024i1_v1024i1_Intrinsic<string GCCIntSuffix>
: Hexagon_Intrinsic<GCCIntSuffix,
[llvm_v1024i1_ty], [llvm_v1024i1_ty],
[IntrNoMem]>;
// V5 Scalar Instructions.
def int_hexagon_S2_asr_r_p_or :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_or">;
def int_hexagon_S2_vsatwh :
Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsatwh">;
def int_hexagon_S2_tableidxd_goodsyntax :
Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxd_goodsyntax">;
def int_hexagon_M2_mpysu_up :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysu_up">;
def int_hexagon_M2_mpyud_acc_ll_s0 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s0">;
def int_hexagon_M2_mpyud_acc_ll_s1 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s1">;
def int_hexagon_M2_cmpysc_s1 :
Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpysc_s1">;
def int_hexagon_M2_cmpysc_s0 :
Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpysc_s0">;
def int_hexagon_M4_cmpyi_whc :
Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_whc">;
def int_hexagon_M2_mpy_sat_rnd_lh_s1 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s1">;
def int_hexagon_M2_mpy_sat_rnd_lh_s0 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s0">;
def int_hexagon_S2_tableidxb_goodsyntax :
Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxb_goodsyntax">;
def int_hexagon_S2_shuffoh :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffoh">;
def int_hexagon_F2_sfmax :
Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmax">;
def int_hexagon_A2_vabswsat :
Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabswsat">;
def int_hexagon_S2_asr_i_r :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r", [ImmArg<1>]>;
def int_hexagon_S2_asr_i_p :
Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p", [ImmArg<1>]>;
def int_hexagon_A4_combineri :
Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineri", [ImmArg<1>]>;
def int_hexagon_M2_mpy_nac_sat_hl_s1 :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s1">;
def int_hexagon_M4_vpmpyh_acc :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_vpmpyh_acc">;
def int_hexagon_M2_vcmpy_s0_sat_i :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_i">;
def int_hexagon_A2_notp :
Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_notp">;
def int_hexagon_M2_mpy_hl_s1 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hl_s1">;
def int_hexagon_M2_mpy_hl_s0 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hl_s0">;
def int_hexagon_C4_or_and :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_and">;
def int_hexagon_M2_vmac2s_s0 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2s_s0">;
def int_hexagon_M2_vmac2s_s1 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2s_s1">;
def int_hexagon_S2_brevp :
Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_brevp">;
def int_hexagon_M4_pmpyw_acc :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_pmpyw_acc">;
def int_hexagon_S2_cl1 :
Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_cl1">;
def int_hexagon_C4_cmplte :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplte">;
def int_hexagon_M2_mmpyul_s0 :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_s0">;
def int_hexagon_A2_vaddws :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddws">;
def int_hexagon_A2_maxup :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxup">;
def int_hexagon_A4_vcmphgti :
Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgti", [ImmArg<1>]>;
def int_hexagon_S2_interleave :
Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_interleave">;
def int_hexagon_M2_vrcmpyi_s0 :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0">;
def int_hexagon_A2_abssat :
Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abssat">;
def int_hexagon_A2_vcmpwgtu :
Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpwgtu">;
def int_hexagon_C2_cmpgtu :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtu">;
def int_hexagon_C2_cmpgtp :
Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtp">;
def int_hexagon_A4_cmphgtui :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtui", [ImmArg<1>]>;
def int_hexagon_C2_cmpgti :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgti", [ImmArg<1>]>;
def int_hexagon_M2_mpyi :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyi">;
def int_hexagon_F2_conv_df2uw_chop :
Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw_chop">;
def int_hexagon_A4_cmpheq :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheq">;
def int_hexagon_M2_mpy_lh_s1 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s1">;
def int_hexagon_M2_mpy_lh_s0 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s0">;
def int_hexagon_S2_lsr_i_r_xacc :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_xacc", [ImmArg<2>]>;
def int_hexagon_S2_vrcnegh :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vrcnegh">;
def int_hexagon_S2_extractup :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S2_extractup", [ImmArg<1>, ImmArg<2>]>;
def int_hexagon_S2_asr_i_p_rnd_goodsyntax :
Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd_goodsyntax", [ImmArg<1>]>;
def int_hexagon_S4_ntstbit_r :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_r">;
def int_hexagon_F2_conv_w2sf :
Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_w2sf">;
def int_hexagon_C2_not :
Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_not">;
def int_hexagon_C2_tfrpr :
Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_tfrpr">;
def int_hexagon_M2_mpy_ll_s1 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_ll_s1">;
def int_hexagon_M2_mpy_ll_s0 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_ll_s0">;
def int_hexagon_A4_cmpbgt :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgt">;
def int_hexagon_S2_asr_r_r_and :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_and">;
def int_hexagon_A4_rcmpneqi :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneqi", [ImmArg<1>]>;
def int_hexagon_S2_asl_i_r_nac :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_nac", [ImmArg<2>]>;
def int_hexagon_M2_subacc :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_subacc">;
def int_hexagon_A2_orp :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_orp">;
def int_hexagon_M2_mpyu_up :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_up">;
def int_hexagon_M2_mpy_acc_sat_lh_s1 :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s1">;
def int_hexagon_S2_asr_i_vh :
Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vh", [ImmArg<1>]>;
def int_hexagon_S2_asr_i_vw :
Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vw", [ImmArg<1>]>;
def int_hexagon_A4_cmpbgtu :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtu">;
def int_hexagon_A4_vcmpbeq_any :
Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbeq_any">;
def int_hexagon_A4_cmpbgti :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgti", [ImmArg<1>]>;
def int_hexagon_M2_mpyd_lh_s1 :
Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s1">;
def int_hexagon_S2_asl_r_p_nac :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_nac">;
def int_hexagon_S2_lsr_i_r_nac :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_nac", [ImmArg<2>]>;
def int_hexagon_A2_addsp :
Hexagon_i64_i32i64_Intrinsic<"HEXAGON_A2_addsp">;
def int_hexagon_S4_vxsubaddw :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddw">;
def int_hexagon_A4_vcmpheqi :
Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpheqi", [ImmArg<1>]>;
def int_hexagon_S4_vxsubaddh :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddh">;
def int_hexagon_M4_pmpyw :
Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_pmpyw">;
def int_hexagon_S2_vsathb :
Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsathb">;
def int_hexagon_S2_asr_r_p_and :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_and">;
def int_hexagon_M2_mpyu_acc_lh_s1 :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s1">;
def int_hexagon_M2_mpyu_acc_lh_s0 :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s0">;
def int_hexagon_S2_lsl_r_p_acc :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_acc">;
def int_hexagon_A2_pxorf :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_A2_pxorf">;
def int_hexagon_C2_cmpgei :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgei", [ImmArg<1>]>;
def int_hexagon_A2_vsubub :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubub">;
def int_hexagon_S2_asl_i_p :
Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_p", [ImmArg<1>]>;
def int_hexagon_S2_asl_i_r :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r", [ImmArg<1>]>;
def int_hexagon_A4_vrminuw :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuw">;
def int_hexagon_F2_sffma :
Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma">;
def int_hexagon_A2_absp :
Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_absp">;
def int_hexagon_C2_all8 :
Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_all8">;
def int_hexagon_A4_vrminuh :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuh">;
def int_hexagon_F2_sffma_lib :
Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma_lib">;
def int_hexagon_M4_vrmpyoh_s0 :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s0">;
def int_hexagon_M4_vrmpyoh_s1 :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s1">;
def int_hexagon_C2_bitsset :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsset">;
def int_hexagon_M2_mpysip :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysip", [ImmArg<1>]>;
def int_hexagon_M2_mpysin :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysin", [ImmArg<1>]>;
def int_hexagon_A4_boundscheck :
Hexagon_i32_i32i64_Intrinsic<"HEXAGON_A4_boundscheck">;
def int_hexagon_M5_vrmpybuu :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybuu">;
def int_hexagon_C4_fastcorner9 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_fastcorner9">;
def int_hexagon_M2_vrcmpys_s1rp :
Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_s1rp">;
def int_hexagon_A2_neg :
Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_neg">;
def int_hexagon_A2_subsat :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subsat">;
def int_hexagon_S2_asl_r_r :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_r_r">;
def int_hexagon_S2_asl_r_p :
Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_p">;
def int_hexagon_A2_vnavgh :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgh">;
def int_hexagon_M2_mpy_nac_sat_hl_s0 :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s0">;
def int_hexagon_F2_conv_ud2df :
Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_ud2df">;
def int_hexagon_A2_vnavgw :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgw">;
def int_hexagon_S2_asl_i_r_acc :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_acc", [ImmArg<2>]>;
def int_hexagon_S4_subi_lsr_ri :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_lsr_ri", [ImmArg<0>, ImmArg<2>]>;
def int_hexagon_S2_vzxthw :
Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxthw">;
def int_hexagon_F2_sfadd :
Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfadd">;
def int_hexagon_A2_sub :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_sub">;
def int_hexagon_M2_vmac2su_s0 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2su_s0">;
def int_hexagon_M2_vmac2su_s1 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2su_s1">;
def int_hexagon_M2_dpmpyss_s0 :
Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_s0">;
def int_hexagon_S2_insert :
Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_insert">;
def int_hexagon_S2_packhl :
Hexagon_i64_i32i32_Intrinsic<"HEXAGON_S2_packhl">;
def int_hexagon_A4_vcmpwgti :
Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgti", [ImmArg<1>]>;
def int_hexagon_A2_vavguwr :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguwr">;
def int_hexagon_S2_asl_r_r_and :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_and">;
def int_hexagon_A2_svsubhs :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubhs">;
def int_hexagon_A2_addh_l16_hl :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_hl">;
def int_hexagon_M4_and_and :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_and">;
def int_hexagon_F2_conv_d2df :
Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_d2df">;
def int_hexagon_C2_cmpgtui :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtui", [ImmArg<1>]>;
def int_hexagon_A2_vconj :
Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vconj">;
def int_hexagon_S2_lsr_r_vw :
Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vw">;
def int_hexagon_S2_lsr_r_vh :
Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vh">;
def int_hexagon_A2_subh_l16_hl :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_hl">;
def int_hexagon_S4_vxsubaddhr :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddhr">;
def int_hexagon_S2_clbp :
Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_clbp">;
def int_hexagon_S2_deinterleave :
Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_deinterleave">;
def int_hexagon_C2_any8 :
Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_any8">;
def int_hexagon_S2_togglebit_r :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_r">;
def int_hexagon_S2_togglebit_i :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_i", [ImmArg<1>]>;
def int_hexagon_F2_conv_uw2sf :
Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_uw2sf">;
def int_hexagon_S2_vsathb_nopack :
Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsathb_nopack">;
def int_hexagon_M2_cmacs_s0 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacs_s0">;
def int_hexagon_M2_cmacs_s1 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacs_s1">;
def int_hexagon_M2_mpy_sat_hh_s0 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s0">;
def int_hexagon_M2_mpy_sat_hh_s1 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s1">;
def int_hexagon_M2_mmacuhs_s1 :
Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_s1">;
def int_hexagon_M2_mmacuhs_s0 :
Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_s0">;
def int_hexagon_S2_clrbit_r :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_r">;
def int_hexagon_C4_or_andn :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_andn">;
def int_hexagon_S2_asl_r_r_nac :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_nac">;
def int_hexagon_S2_asl_i_p_acc :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_acc", [ImmArg<2>]>;
def int_hexagon_A4_vcmpwgtui :
Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgtui", [ImmArg<1>]>;
def int_hexagon_M4_vrmpyoh_acc_s0 :
Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s0">;
def int_hexagon_M4_vrmpyoh_acc_s1 :
Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s1">;
def int_hexagon_A4_vrmaxh :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxh">;
def int_hexagon_A2_vcmpbeq :
Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpbeq">;
def int_hexagon_A2_vcmphgt :
Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgt">;
def int_hexagon_A2_vnavgwcr :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgwcr">;
def int_hexagon_M2_vrcmacr_s0c :
Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0c">;
def int_hexagon_A2_vavgwcr :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwcr">;
def int_hexagon_S2_asl_i_p_xacc :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_xacc", [ImmArg<2>]>;
def int_hexagon_A4_vrmaxw :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxw">;
def int_hexagon_A2_vnavghr :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghr">;
def int_hexagon_M4_cmpyi_wh :
Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_wh">;
def int_hexagon_A2_tfrsi :
Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrsi", [ImmArg<0>]>;
def int_hexagon_S2_asr_i_r_acc :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_acc", [ImmArg<2>]>;
def int_hexagon_A2_svnavgh :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svnavgh">;
def int_hexagon_S2_lsr_i_r :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r", [ImmArg<1>]>;
def int_hexagon_M2_vmac2 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2">;
def int_hexagon_A4_vcmphgtui :
Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgtui", [ImmArg<1>]>;
def int_hexagon_A2_svavgh :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavgh">;
def int_hexagon_M4_vrmpyeh_acc_s0 :
Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s0">;
def int_hexagon_M4_vrmpyeh_acc_s1 :
Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s1">;
def int_hexagon_S2_lsr_i_p :
Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p", [ImmArg<1>]>;
def int_hexagon_A2_combine_hl :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hl">;
def int_hexagon_M2_mpy_up :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up">;
def int_hexagon_A2_combine_hh :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hh">;
def int_hexagon_A2_negsat :
Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_negsat">;
def int_hexagon_M2_mpyd_hl_s0 :
Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hl_s0">;
def int_hexagon_M2_mpyd_hl_s1 :
Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hl_s1">;
def int_hexagon_A4_bitsplit :
Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitsplit">;
def int_hexagon_A2_vabshsat :
Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabshsat">;
def int_hexagon_M2_mpyui :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyui">;
def int_hexagon_A2_addh_l16_sat_ll :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_ll">;
def int_hexagon_S2_lsl_r_r_and :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_and">;
def int_hexagon_M2_mmpyul_rs0 :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs0">;
def int_hexagon_S2_asr_i_r_rnd_goodsyntax :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd_goodsyntax", [ImmArg<1>]>;
def int_hexagon_S2_lsr_r_p_nac :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_nac">;
def int_hexagon_C2_cmplt :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmplt">;
def int_hexagon_M2_cmacr_s0 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacr_s0">;
def int_hexagon_M4_or_and :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_and">;
def int_hexagon_M4_mpyrr_addi :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addi", [ImmArg<0>]>;
def int_hexagon_S4_or_andi :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andi", [ImmArg<2>]>;
def int_hexagon_M2_mpy_sat_hl_s0 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s0">;
def int_hexagon_M2_mpy_sat_hl_s1 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s1">;
def int_hexagon_M4_mpyrr_addr :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addr">;
def int_hexagon_M2_mmachs_rs0 :
Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_rs0">;
def int_hexagon_M2_mmachs_rs1 :
Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_rs1">;
def int_hexagon_M2_vrcmpyr_s0c :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyr_s0c">;
def int_hexagon_M2_mpy_acc_sat_hl_s0 :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s0">;
def int_hexagon_M2_mpyd_acc_ll_s1 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s1">;
def int_hexagon_F2_sffixupn :
Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupn">;
def int_hexagon_M2_mpyd_acc_lh_s0 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s0">;
def int_hexagon_M2_mpyd_acc_lh_s1 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s1">;
def int_hexagon_M2_mpy_rnd_hh_s0 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s0">;
def int_hexagon_M2_mpy_rnd_hh_s1 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s1">;
def int_hexagon_A2_vadduhs :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vadduhs">;
def int_hexagon_A2_vsubuhs :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubuhs">;
def int_hexagon_A2_subh_h16_hl :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hl">;
def int_hexagon_A2_subh_h16_hh :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hh">;
def int_hexagon_A2_xorp :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_xorp">;
def int_hexagon_A4_tfrpcp :
Hexagon_i64_i64_Intrinsic<"HEXAGON_A4_tfrpcp">;
def int_hexagon_A2_addh_h16_lh :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_lh">;
def int_hexagon_A2_addh_h16_sat_hl :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_hl">;
def int_hexagon_A2_addh_h16_ll :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_ll">;
def int_hexagon_A2_addh_h16_sat_hh :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_hh">;
def int_hexagon_A2_zxtb :
Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_zxtb">;
def int_hexagon_A2_zxth :
Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_zxth">;
def int_hexagon_A2_vnavgwr :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgwr">;
def int_hexagon_M4_or_xor :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_xor">;
def int_hexagon_M2_mpyud_acc_hh_s0 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s0">;
def int_hexagon_M2_mpyud_acc_hh_s1 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s1">;
def int_hexagon_M5_vmacbsu :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbsu">;
def int_hexagon_M2_dpmpyuu_acc_s0 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_acc_s0">;
def int_hexagon_M2_mpy_rnd_hl_s0 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s0">;
def int_hexagon_M2_mpy_rnd_hl_s1 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s1">;
def int_hexagon_F2_sffms_lib :
Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms_lib">;
def int_hexagon_C4_cmpneqi :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneqi", [ImmArg<1>]>;
def int_hexagon_M4_and_xor :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_xor">;
def int_hexagon_A2_sat :
Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_sat">;
def int_hexagon_M2_mpyd_nac_lh_s1 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s1">;
def int_hexagon_M2_mpyd_nac_lh_s0 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s0">;
def int_hexagon_A2_addsat :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addsat">;
def int_hexagon_A2_svavghs :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavghs">;
def int_hexagon_A2_vrsadub_acc :
Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vrsadub_acc">;
def int_hexagon_C2_bitsclri :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclri", [ImmArg<1>]>;
def int_hexagon_A2_subh_h16_sat_hh :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hh">;
def int_hexagon_A2_subh_h16_sat_hl :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hl">;
def int_hexagon_M2_mmaculs_rs0 :
Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_rs0">;
def int_hexagon_M2_mmaculs_rs1 :
Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_rs1">;
def int_hexagon_M2_vradduh :
Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vradduh">;
def int_hexagon_A4_addp_c :
Hexagon_i64i32_i64i64i32_Intrinsic<"HEXAGON_A4_addp_c">;
def int_hexagon_C2_xor :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_xor">;
def int_hexagon_S2_lsl_r_r_acc :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_acc">;
def int_hexagon_M2_mmpyh_rs1 :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_rs1">;
def int_hexagon_M2_mmpyh_rs0 :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_rs0">;
def int_hexagon_F2_conv_df2ud_chop :
Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2ud_chop">;
def int_hexagon_C4_or_or :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_or">;
def int_hexagon_S4_vxaddsubhr :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubhr">;
def int_hexagon_S2_vsathub :
Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsathub">;
def int_hexagon_F2_conv_df2sf :
Hexagon_float_double_Intrinsic<"HEXAGON_F2_conv_df2sf">;
def int_hexagon_M2_hmmpyh_rs1 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_rs1">;
def int_hexagon_M2_hmmpyh_s1 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_s1">;
def int_hexagon_A2_vavgwr :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwr">;
def int_hexagon_S2_tableidxh_goodsyntax :
Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxh_goodsyntax">;
def int_hexagon_A2_sxth :
Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sxth">;
def int_hexagon_A2_sxtb :
Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sxtb">;
def int_hexagon_C4_or_orn :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_orn">;
def int_hexagon_M2_vrcmaci_s0c :
Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmaci_s0c">;
def int_hexagon_A2_sxtw :
Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_sxtw">;
def int_hexagon_M2_vabsdiffh :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vabsdiffh">;
def int_hexagon_M2_mpy_acc_lh_s1 :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s1">;
def int_hexagon_M2_mpy_acc_lh_s0 :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s0">;
def int_hexagon_M2_hmmpyl_s1 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyl_s1">;
def int_hexagon_S2_cl1p :
Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl1p">;
def int_hexagon_M2_vabsdiffw :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vabsdiffw">;
def int_hexagon_A4_andnp :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A4_andnp">;
def int_hexagon_C2_vmux :
Hexagon_i64_i32i64i64_Intrinsic<"HEXAGON_C2_vmux">;
def int_hexagon_S2_parityp :
Hexagon_i32_i64i64_Intrinsic<"HEXAGON_S2_parityp">;
def int_hexagon_S2_lsr_i_p_and :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_and", [ImmArg<2>]>;
def int_hexagon_S2_asr_i_r_or :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_or", [ImmArg<2>]>;
def int_hexagon_M2_mpyu_nac_ll_s0 :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s0">;
def int_hexagon_M2_mpyu_nac_ll_s1 :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s1">;
def int_hexagon_F2_sfcmpeq :
Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpeq">;
def int_hexagon_A2_vaddb_map :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddb_map">;
def int_hexagon_S2_lsr_r_r_nac :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_nac">;
def int_hexagon_A2_vcmpheq :
Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpheq">;
def int_hexagon_S2_clbnorm :
Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_clbnorm">;
def int_hexagon_M2_cnacsc_s1 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacsc_s1">;
def int_hexagon_M2_cnacsc_s0 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacsc_s0">;
def int_hexagon_S4_subaddi :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subaddi", [ImmArg<1>]>;
def int_hexagon_M2_mpyud_nac_hl_s1 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s1">;
def int_hexagon_M2_mpyud_nac_hl_s0 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s0">;
def int_hexagon_S5_vasrhrnd_goodsyntax :
Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S5_vasrhrnd_goodsyntax", [ImmArg<1>]>;
def int_hexagon_S2_tstbit_r :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_r">;
def int_hexagon_S4_vrcrotate :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate", [ImmArg<2>]>;
def int_hexagon_M2_mmachs_s1 :
Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s1">;
def int_hexagon_M2_mmachs_s0 :
Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s0">;
def int_hexagon_S2_tstbit_i :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_i", [ImmArg<1>]>;
def int_hexagon_M2_mpy_up_s1 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1">;
def int_hexagon_S2_extractu_rp :
Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S2_extractu_rp">;
def int_hexagon_M2_mmpyuh_rs0 :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs0">;
def int_hexagon_S2_lsr_i_vw :
Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vw", [ImmArg<1>]>;
def int_hexagon_M2_mpy_rnd_ll_s0 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s0">;
def int_hexagon_M2_mpy_rnd_ll_s1 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s1">;
def int_hexagon_M4_or_or :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_or">;
def int_hexagon_M2_mpyu_hh_s1 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hh_s1">;
def int_hexagon_M2_mpyu_hh_s0 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hh_s0">;
def int_hexagon_S2_asl_r_p_acc :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_acc">;
def int_hexagon_M2_mpyu_nac_lh_s0 :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s0">;
def int_hexagon_M2_mpyu_nac_lh_s1 :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s1">;
def int_hexagon_M2_mpy_sat_ll_s0 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s0">;
def int_hexagon_M2_mpy_sat_ll_s1 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s1">;
def int_hexagon_F2_conv_w2df :
Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_w2df">;
def int_hexagon_A2_subh_l16_sat_hl :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_hl">;
def int_hexagon_C2_cmpeqi :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpeqi", [ImmArg<1>]>;
def int_hexagon_S2_asl_i_r_and :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_and", [ImmArg<2>]>;
def int_hexagon_S2_vcnegh :
Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcnegh">;
def int_hexagon_A4_vcmpweqi :
Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpweqi", [ImmArg<1>]>;
def int_hexagon_M2_vdmpyrs_s0 :
Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s0">;
def int_hexagon_M2_vdmpyrs_s1 :
Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s1">;
def int_hexagon_M4_xor_xacc :
Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_xor_xacc">;
def int_hexagon_M2_vdmpys_s1 :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vdmpys_s1">;
def int_hexagon_M2_vdmpys_s0 :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vdmpys_s0">;
def int_hexagon_A2_vavgubr :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgubr">;
def int_hexagon_M2_mpyu_hl_s1 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hl_s1">;
def int_hexagon_M2_mpyu_hl_s0 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hl_s0">;
def int_hexagon_S2_asl_r_r_acc :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_acc">;
def int_hexagon_S2_cl0p :
Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl0p">;
def int_hexagon_S2_valignib :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignib", [ImmArg<2>]>;
def int_hexagon_F2_sffixupd :
Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupd">;
def int_hexagon_M2_mpy_sat_rnd_hl_s1 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s1">;
def int_hexagon_M2_mpy_sat_rnd_hl_s0 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s0">;
def int_hexagon_M2_cmacsc_s0 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacsc_s0">;
def int_hexagon_M2_cmacsc_s1 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacsc_s1">;
def int_hexagon_S2_ct1 :
Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_ct1">;
def int_hexagon_S2_ct0 :
Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_ct0">;
def int_hexagon_M2_dpmpyuu_nac_s0 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_nac_s0">;
def int_hexagon_M2_mmpyul_rs1 :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs1">;
def int_hexagon_S4_ntstbit_i :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_i", [ImmArg<1>]> ;
def int_hexagon_F2_sffixupr :
Hexagon_float_float_Intrinsic<"HEXAGON_F2_sffixupr">;
def int_hexagon_S2_asr_r_p_xor :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_xor">;
def int_hexagon_M2_mpyud_acc_hl_s0 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s0">;
def int_hexagon_M2_mpyud_acc_hl_s1 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s1">;
def int_hexagon_A2_vcmphgtu :
Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgtu">;
def int_hexagon_C2_andn :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_andn">;
def int_hexagon_M2_vmpy2s_s0pack :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0pack">;
def int_hexagon_S4_addaddi :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addaddi", [ImmArg<2>]>;
def int_hexagon_M2_mpyd_acc_ll_s0 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s0">;
def int_hexagon_M2_mpy_acc_sat_hl_s1 :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s1">;
def int_hexagon_A4_rcmpeqi :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeqi", [ImmArg<1>]>;
def int_hexagon_M4_xor_and :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_and">;
def int_hexagon_S2_asl_i_p_and :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_and", [ImmArg<2>]>;
def int_hexagon_M2_mmpyuh_rs1 :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs1">;
def int_hexagon_S2_asr_r_r_or :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_or">;
def int_hexagon_A4_round_ri :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri", [ImmArg<1>]>;
def int_hexagon_A2_max :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_max">;
def int_hexagon_A4_round_rr :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr">;
def int_hexagon_A4_combineii :
Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineii", [ImmArg<0>, ImmArg<1>]>;
def int_hexagon_A4_combineir :
Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineir", [ImmArg<0>]>;
def int_hexagon_C4_and_orn :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_orn">;
def int_hexagon_M5_vmacbuu :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbuu">;
def int_hexagon_A4_rcmpeq :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeq">;
def int_hexagon_M4_cmpyr_whc :
Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_whc">;
def int_hexagon_S2_lsr_i_r_acc :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_acc", [ImmArg<2>]>;
def int_hexagon_S2_vzxtbh :
Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxtbh">;
def int_hexagon_M2_mmacuhs_rs1 :
Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_rs1">;
def int_hexagon_S2_asr_r_r_sat :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_sat">;
def int_hexagon_A2_combinew :
Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combinew">;
def int_hexagon_M2_mpy_acc_ll_s1 :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s1">;
def int_hexagon_M2_mpy_acc_ll_s0 :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s0">;
def int_hexagon_M2_cmpyi_s0 :
Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyi_s0">;
def int_hexagon_S2_asl_r_p_or :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_or">;
def int_hexagon_S4_ori_asl_ri :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_asl_ri", [ImmArg<0>, ImmArg<2>]>;
def int_hexagon_C4_nbitsset :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsset">;
def int_hexagon_M2_mpyu_acc_hh_s1 :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s1">;
def int_hexagon_M2_mpyu_acc_hh_s0 :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s0">;
def int_hexagon_M2_mpyu_ll_s1 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_ll_s1">;
def int_hexagon_M2_mpyu_ll_s0 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_ll_s0">;
def int_hexagon_A2_addh_l16_ll :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_ll">;
def int_hexagon_S2_lsr_r_r_and :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_and">;
def int_hexagon_A4_modwrapu :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_modwrapu">;
def int_hexagon_A4_rcmpneq :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneq">;
def int_hexagon_M2_mpyd_acc_hh_s0 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s0">;
def int_hexagon_M2_mpyd_acc_hh_s1 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s1">;
def int_hexagon_F2_sfimm_p :
Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_p", [ImmArg<0>]>;
def int_hexagon_F2_sfimm_n :
Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_n", [ImmArg<0>]>;
def int_hexagon_M4_cmpyr_wh :
Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_wh">;
def int_hexagon_S2_lsl_r_p_and :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_and">;
def int_hexagon_A2_vavgub :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgub">;
def int_hexagon_F2_conv_d2sf :
Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_d2sf">;
def int_hexagon_A2_vavguh :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguh">;
def int_hexagon_A4_cmpbeqi :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeqi", [ImmArg<1>]>;
def int_hexagon_F2_sfcmpuo :
Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpuo">;
def int_hexagon_A2_vavguw :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguw">;
def int_hexagon_S2_asr_i_p_nac :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_nac", [ImmArg<2>]>;
def int_hexagon_S2_vsatwh_nopack :
Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsatwh_nopack">;
def int_hexagon_M2_mpyd_hh_s0 :
Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s0">;
def int_hexagon_M2_mpyd_hh_s1 :
Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s1">;
def int_hexagon_S2_lsl_r_p_or :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_or">;
def int_hexagon_A2_minu :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_minu">;
def int_hexagon_M2_mpy_sat_lh_s1 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s1">;
def int_hexagon_M4_or_andn :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_andn">;
def int_hexagon_A2_minp :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minp">;
def int_hexagon_S4_or_andix :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andix", [ImmArg<2>]>;
def int_hexagon_M2_mpy_rnd_lh_s0 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s0">;
def int_hexagon_M2_mpy_rnd_lh_s1 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s1">;
def int_hexagon_M2_mmpyuh_s0 :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_s0">;
def int_hexagon_M2_mmpyuh_s1 :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_s1">;
def int_hexagon_M2_mpy_acc_sat_lh_s0 :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s0">;
def int_hexagon_F2_sfcmpge :
Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpge">;
def int_hexagon_F2_sfmin :
Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmin">;
def int_hexagon_F2_sfcmpgt :
Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpgt">;
def int_hexagon_M4_vpmpyh :
Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_vpmpyh">;
def int_hexagon_M2_mmacuhs_rs0 :
Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_rs0">;
def int_hexagon_M2_mpyd_rnd_lh_s1 :
Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s1">;
def int_hexagon_M2_mpyd_rnd_lh_s0 :
Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s0">;
def int_hexagon_A2_roundsat :
Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_roundsat">;
def int_hexagon_S2_ct1p :
Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_ct1p">;
def int_hexagon_S4_extract_rp :
Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S4_extract_rp">;
def int_hexagon_S2_lsl_r_r_or :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_or">;
def int_hexagon_C4_cmplteui :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteui", [ImmArg<1>]>;
def int_hexagon_S4_addi_lsr_ri :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_lsr_ri", [ImmArg<0>, ImmArg<2>]>;
def int_hexagon_A4_tfrcpp :
Hexagon_i64_i64_Intrinsic<"HEXAGON_A4_tfrcpp">;
def int_hexagon_S2_asr_i_svw_trun :
Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S2_asr_i_svw_trun", [ImmArg<1>]>;
def int_hexagon_A4_cmphgti :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgti", [ImmArg<1>]>;
def int_hexagon_A4_vrminh :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminh">;
def int_hexagon_A4_vrminw :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminw">;
def int_hexagon_A4_cmphgtu :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtu">;
def int_hexagon_S2_insertp_rp :
Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_S2_insertp_rp">;
def int_hexagon_A2_vnavghcr :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghcr">;
def int_hexagon_S4_subi_asl_ri :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_asl_ri", [ImmArg<0>, ImmArg<2>]>;
def int_hexagon_S2_lsl_r_vh :
Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vh">;
def int_hexagon_M2_mpy_hh_s0 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s0">;
def int_hexagon_A2_vsubws :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubws">;
def int_hexagon_A2_sath :
Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sath">;
def int_hexagon_S2_asl_r_p_xor :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_xor">;
def int_hexagon_A2_satb :
Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satb">;
def int_hexagon_C2_cmpltu :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpltu">;
def int_hexagon_S2_insertp :
Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S2_insertp", [ImmArg<2>, ImmArg<3>]>;
def int_hexagon_M2_mpyd_rnd_ll_s1 :
Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s1">;
def int_hexagon_M2_mpyd_rnd_ll_s0 :
Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s0">;
def int_hexagon_S2_lsr_i_p_nac :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_nac", [ImmArg<2>]>;
def int_hexagon_S2_extractup_rp :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_extractup_rp">;
def int_hexagon_S4_vxaddsubw :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubw">;
def int_hexagon_S4_vxaddsubh :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubh">;
def int_hexagon_A2_asrh :
Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_asrh">;
def int_hexagon_S4_extractp_rp :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_extractp_rp">;
def int_hexagon_S2_lsr_r_r_acc :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_acc">;
def int_hexagon_M2_mpyd_nac_ll_s1 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s1">;
def int_hexagon_M2_mpyd_nac_ll_s0 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s0">;
def int_hexagon_C2_or :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_or">;
def int_hexagon_M2_mmpyul_s1 :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_s1">;
def int_hexagon_M2_vrcmacr_s0 :
Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0">;
def int_hexagon_A2_xor :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_xor">;
def int_hexagon_A2_add :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_add">;
def int_hexagon_A2_vsububs :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsububs">;
def int_hexagon_M2_vmpy2s_s1 :
Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s1">;
def int_hexagon_M2_vmpy2s_s0 :
Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0">;
def int_hexagon_A2_vraddub_acc :
Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vraddub_acc">;
def int_hexagon_F2_sfinvsqrta :
Hexagon_floati32_float_Intrinsic<"HEXAGON_F2_sfinvsqrta">;
def int_hexagon_S2_ct0p :
Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_ct0p">;
def int_hexagon_A2_svaddh :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svaddh">;
def int_hexagon_S2_vcrotate :
Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcrotate">;
def int_hexagon_A2_aslh :
Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_aslh">;
def int_hexagon_A2_subh_h16_lh :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_lh">;
def int_hexagon_A2_subh_h16_ll :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_ll">;
def int_hexagon_M2_hmmpyl_rs1 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyl_rs1">;
def int_hexagon_S2_asr_r_p :
Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_p">;
def int_hexagon_S2_vsplatrh :
Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsplatrh">;
def int_hexagon_S2_asr_r_r :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_r_r">;
def int_hexagon_A2_addh_h16_hl :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hl">;
def int_hexagon_S2_vsplatrb :
Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_vsplatrb">;
def int_hexagon_A2_addh_h16_hh :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hh">;
def int_hexagon_M2_cmpyr_s0 :
Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyr_s0">;
def int_hexagon_M2_dpmpyss_rnd_s0 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_rnd_s0">;
def int_hexagon_C2_muxri :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxri", [ImmArg<1>]>;
def int_hexagon_M2_vmac2es_s0 :
Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s0">;
def int_hexagon_M2_vmac2es_s1 :
Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s1">;
def int_hexagon_C2_pxfer_map :
Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_pxfer_map">;
def int_hexagon_M2_mpyu_lh_s1 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s1">;
def int_hexagon_M2_mpyu_lh_s0 :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s0">;
def int_hexagon_S2_asl_i_r_or :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_or", [ImmArg<2>]>;
def int_hexagon_M2_mpyd_acc_hl_s0 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s0">;
def int_hexagon_M2_mpyd_acc_hl_s1 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s1">;
def int_hexagon_S2_asr_r_p_nac :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_nac">;
def int_hexagon_A2_vaddw :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddw">;
def int_hexagon_S2_asr_i_r_and :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_and", [ImmArg<2>]>;
def int_hexagon_A2_vaddh :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddh">;
def int_hexagon_M2_mpy_nac_sat_lh_s1 :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s1">;
def int_hexagon_M2_mpy_nac_sat_lh_s0 :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s0">;
def int_hexagon_C2_cmpeqp :
Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpeqp">;
def int_hexagon_M4_mpyri_addi :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addi", [ImmArg<0>, ImmArg<2>]>;
def int_hexagon_A2_not :
Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_not">;
def int_hexagon_S4_andi_lsr_ri :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_lsr_ri", [ImmArg<0>, ImmArg<2>]>;
def int_hexagon_M2_macsip :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsip", [ImmArg<2>]>;
def int_hexagon_A2_tfrcrr :
Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrcrr">;
def int_hexagon_M2_macsin :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsin", [ImmArg<2>]>;
def int_hexagon_C2_orn :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_orn">;
def int_hexagon_M4_and_andn :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_andn">;
def int_hexagon_F2_sfmpy :
Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmpy">;
def int_hexagon_M2_mpyud_nac_hh_s1 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s1">;
def int_hexagon_M2_mpyud_nac_hh_s0 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s0">;
def int_hexagon_S2_lsr_r_p_acc :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_acc">;
def int_hexagon_S2_asr_r_vw :
Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_vw">;
def int_hexagon_M4_and_or :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_or">;
def int_hexagon_S2_asr_r_vh :
Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_vh">;
def int_hexagon_C2_mask :
Hexagon_i64_i32_Intrinsic<"HEXAGON_C2_mask">;
def int_hexagon_M2_mpy_nac_hh_s0 :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s0">;
def int_hexagon_M2_mpy_nac_hh_s1 :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s1">;
def int_hexagon_M2_mpy_up_s1_sat :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1_sat">;
def int_hexagon_A4_vcmpbgt :
Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbgt">;
def int_hexagon_M5_vrmacbsu :
Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vrmacbsu">;
def int_hexagon_S2_tableidxw_goodsyntax :
Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxw_goodsyntax">;
def int_hexagon_A2_vrsadub :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vrsadub">;
def int_hexagon_A2_tfrrcr :
Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrrcr">;
def int_hexagon_M2_vrcmpys_acc_s1 :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_acc_s1">;
def int_hexagon_F2_dfcmpge :
Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpge">;
def int_hexagon_M2_accii :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_accii", [ImmArg<2>]>;
def int_hexagon_A5_vaddhubs :
Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A5_vaddhubs">;
def int_hexagon_A2_vmaxw :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxw">;
def int_hexagon_A2_vmaxb :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxb">;
def int_hexagon_A2_vmaxh :
Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxh">;
def int_hexagon_S2_vsxthw :
Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxthw">;
def int_hexagon_S4_andi_asl_ri :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_asl_ri", [ImmArg<0>, ImmArg<2>]>;
def int_hexagon_S2_asl_i_p_nac :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_nac", [ImmArg<2>]>;
def int_hexagon_S2_lsl_r_p_xor :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_xor">;
def int_hexagon_C2_cmpgt :
Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgt">;
def int_hexagon_F2_conv_df2d_chop :
Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2d_chop">;
def int_hexagon_M2_mpyu_nac_hl_s0 :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s0">;
def int_hexagon_M2_mpyu_nac_hl_s1 :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s1">;
def int_hexagon_F2_conv_sf2w :
Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2w">;
def int_hexagon_S2_lsr_r_p_or :
Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_or">;
def int_hexagon_F2_sfclass :
Hexagon_i32_floati32_Intrinsic<"HEXAGON_F2_sfclass">;
def int_hexagon_M2_mpyud_acc_lh_s0 :
Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s0">;
def int_hexagon_M4_xor_andn :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_andn">;
def int_hexagon_S2_addasl_rrri :
Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_addasl_rrri",