| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2 |
| ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ssse3 | FileCheck %s --check-prefixes=SSE,SSSE3 |
| ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41 |
| ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1 |
| ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2 |
| ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl,+fast-variable-shuffle | FileCheck %s --check-prefixes=AVX,AVX512 |
| |
| declare <1 x i8> @llvm.usub.sat.v1i8(<1 x i8>, <1 x i8>) |
| declare <2 x i8> @llvm.usub.sat.v2i8(<2 x i8>, <2 x i8>) |
| declare <4 x i8> @llvm.usub.sat.v4i8(<4 x i8>, <4 x i8>) |
| declare <8 x i8> @llvm.usub.sat.v8i8(<8 x i8>, <8 x i8>) |
| declare <12 x i8> @llvm.usub.sat.v12i8(<12 x i8>, <12 x i8>) |
| declare <16 x i8> @llvm.usub.sat.v16i8(<16 x i8>, <16 x i8>) |
| declare <32 x i8> @llvm.usub.sat.v32i8(<32 x i8>, <32 x i8>) |
| declare <64 x i8> @llvm.usub.sat.v64i8(<64 x i8>, <64 x i8>) |
| |
| declare <1 x i16> @llvm.usub.sat.v1i16(<1 x i16>, <1 x i16>) |
| declare <2 x i16> @llvm.usub.sat.v2i16(<2 x i16>, <2 x i16>) |
| declare <4 x i16> @llvm.usub.sat.v4i16(<4 x i16>, <4 x i16>) |
| declare <8 x i16> @llvm.usub.sat.v8i16(<8 x i16>, <8 x i16>) |
| declare <12 x i16> @llvm.usub.sat.v12i16(<12 x i16>, <12 x i16>) |
| declare <16 x i16> @llvm.usub.sat.v16i16(<16 x i16>, <16 x i16>) |
| declare <32 x i16> @llvm.usub.sat.v32i16(<32 x i16>, <32 x i16>) |
| |
| declare <16 x i1> @llvm.usub.sat.v16i1(<16 x i1>, <16 x i1>) |
| declare <16 x i4> @llvm.usub.sat.v16i4(<16 x i4>, <16 x i4>) |
| |
| declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>) |
| declare <2 x i32> @llvm.usub.sat.v2i32(<2 x i32>, <2 x i32>) |
| declare <4 x i24> @llvm.usub.sat.v4i24(<4 x i24>, <4 x i24>) |
| declare <2 x i128> @llvm.usub.sat.v2i128(<2 x i128>, <2 x i128>) |
| |
| ; Legal types, depending on architecture. |
| |
| define <16 x i8> @v16i8(<16 x i8> %x, <16 x i8> %y) nounwind { |
| ; SSE-LABEL: v16i8: |
| ; SSE: # %bb.0: |
| ; SSE-NEXT: psubusb %xmm1, %xmm0 |
| ; SSE-NEXT: retq |
| ; |
| ; AVX-LABEL: v16i8: |
| ; AVX: # %bb.0: |
| ; AVX-NEXT: vpsubusb %xmm1, %xmm0, %xmm0 |
| ; AVX-NEXT: retq |
| %z = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %x, <16 x i8> %y) |
| ret <16 x i8> %z |
| } |
| |
| define <32 x i8> @v32i8(<32 x i8> %x, <32 x i8> %y) nounwind { |
| ; SSE-LABEL: v32i8: |
| ; SSE: # %bb.0: |
| ; SSE-NEXT: psubusb %xmm2, %xmm0 |
| ; SSE-NEXT: psubusb %xmm3, %xmm1 |
| ; SSE-NEXT: retq |
| ; |
| ; AVX1-LABEL: v32i8: |
| ; AVX1: # %bb.0: |
| ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 |
| ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 |
| ; AVX1-NEXT: vpsubusb %xmm2, %xmm3, %xmm2 |
| ; AVX1-NEXT: vpsubusb %xmm1, %xmm0, %xmm0 |
| ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 |
| ; AVX1-NEXT: retq |
| ; |
| ; AVX2-LABEL: v32i8: |
| ; AVX2: # %bb.0: |
| ; AVX2-NEXT: vpsubusb %ymm1, %ymm0, %ymm0 |
| ; AVX2-NEXT: retq |
| ; |
| ; AVX512-LABEL: v32i8: |
| ; AVX512: # %bb.0: |
| ; AVX512-NEXT: vpsubusb %ymm1, %ymm0, %ymm0 |
| ; AVX512-NEXT: retq |
| %z = call <32 x i8> @llvm.usub.sat.v32i8(<32 x i8> %x, <32 x i8> %y) |
| ret <32 x i8> %z |
| } |
| |
| define <64 x i8> @v64i8(<64 x i8> %x, <64 x i8> %y) nounwind { |
| ; SSE-LABEL: v64i8: |
| ; SSE: # %bb.0: |
| ; SSE-NEXT: psubusb %xmm4, %xmm0 |
| ; SSE-NEXT: psubusb %xmm5, %xmm1 |
| ; SSE-NEXT: psubusb %xmm6, %xmm2 |
| ; SSE-NEXT: psubusb %xmm7, %xmm3 |
| ; SSE-NEXT: retq |
| ; |
| ; AVX1-LABEL: v64i8: |
| ; AVX1: # %bb.0: |
| ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4 |
| ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm5 |
| ; AVX1-NEXT: vpsubusb %xmm4, %xmm5, %xmm4 |
| ; AVX1-NEXT: vpsubusb %xmm2, %xmm0, %xmm0 |
| ; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0 |
| ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm2 |
| ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4 |
| ; AVX1-NEXT: vpsubusb %xmm2, %xmm4, %xmm2 |
| ; AVX1-NEXT: vpsubusb %xmm3, %xmm1, %xmm1 |
| ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 |
| ; AVX1-NEXT: retq |
| ; |
| ; AVX2-LABEL: v64i8: |
| ; AVX2: # %bb.0: |
| ; AVX2-NEXT: vpsubusb %ymm2, %ymm0, %ymm0 |
| ; AVX2-NEXT: vpsubusb %ymm3, %ymm1, %ymm1 |
| ; AVX2-NEXT: retq |
| ; |
| ; AVX512-LABEL: v64i8: |
| ; AVX512: # %bb.0: |
| ; AVX512-NEXT: vpsubusb %zmm1, %zmm0, %zmm0 |
| ; AVX512-NEXT: retq |
| %z = call <64 x i8> @llvm.usub.sat.v64i8(<64 x i8> %x, <64 x i8> %y) |
| ret <64 x i8> %z |
| } |
| |
| define <8 x i16> @v8i16(<8 x i16> %x, <8 x i16> %y) nounwind { |
| ; SSE-LABEL: v8i16: |
| ; SSE: # %bb.0: |
| ; SSE-NEXT: psubusw %xmm1, %xmm0 |
| ; SSE-NEXT: retq |
| ; |
| ; AVX-LABEL: v8i16: |
| ; AVX: # %bb.0: |
| ; AVX-NEXT: vpsubusw %xmm1, %xmm0, %xmm0 |
| ; AVX-NEXT: retq |
| %z = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %x, <8 x i16> %y) |
| ret <8 x i16> %z |
| } |
| |
| define <16 x i16> @v16i16(<16 x i16> %x, <16 x i16> %y) nounwind { |
| ; SSE-LABEL: v16i16: |
| ; SSE: # %bb.0: |
| ; SSE-NEXT: psubusw %xmm2, %xmm0 |
| ; SSE-NEXT: psubusw %xmm3, %xmm1 |
| ; SSE-NEXT: retq |
| ; |
| ; AVX1-LABEL: v16i16: |
| ; AVX1: # %bb.0: |
| ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 |
| ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 |
| ; AVX1-NEXT: vpsubusw %xmm2, %xmm3, %xmm2 |
| ; AVX1-NEXT: vpsubusw %xmm1, %xmm0, %xmm0 |
| ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 |
| ; AVX1-NEXT: retq |
| ; |
| ; AVX2-LABEL: v16i16: |
| ; AVX2: # %bb.0: |
| ; AVX2-NEXT: vpsubusw %ymm1, %ymm0, %ymm0 |
| ; AVX2-NEXT: retq |
| ; |
| ; AVX512-LABEL: v16i16: |
| ; AVX512: # %bb.0: |
| ; AVX512-NEXT: vpsubusw %ymm1, %ymm0, %ymm0 |
| ; AVX512-NEXT: retq |
| %z = call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> %x, <16 x i16> %y) |
| ret <16 x i16> %z |
| } |
| |
| define <32 x i16> @v32i16(<32 x i16> %x, <32 x i16> %y) nounwind { |
| ; SSE-LABEL: v32i16: |
| ; SSE: # %bb.0: |
| ; SSE-NEXT: psubusw %xmm4, %xmm0 |
| ; SSE-NEXT: psubusw %xmm5, %xmm1 |
| ; SSE-NEXT: psubusw %xmm6, %xmm2 |
| ; SSE-NEXT: psubusw %xmm7, %xmm3 |
| ; SSE-NEXT: retq |
| ; |
| ; AVX1-LABEL: v32i16: |
| ; AVX1: # %bb.0: |
| ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4 |
| ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm5 |
| ; AVX1-NEXT: vpsubusw %xmm4, %xmm5, %xmm4 |
| ; AVX1-NEXT: vpsubusw %xmm2, %xmm0, %xmm0 |
| ; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0 |
| ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm2 |
| ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4 |
| ; AVX1-NEXT: vpsubusw %xmm2, %xmm4, %xmm2 |
| ; AVX1-NEXT: vpsubusw %xmm3, %xmm1, %xmm1 |
| ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 |
| ; AVX1-NEXT: retq |
| ; |
| ; AVX2-LABEL: v32i16: |
| ; AVX2: # %bb.0: |
| ; AVX2-NEXT: vpsubusw %ymm2, %ymm0, %ymm0 |
| ; AVX2-NEXT: vpsubusw %ymm3, %ymm1, %ymm1 |
| ; AVX2-NEXT: retq |
| ; |
| ; AVX512-LABEL: v32i16: |
| ; AVX512: # %bb.0: |
| ; AVX512-NEXT: vpsubusw %zmm1, %zmm0, %zmm0 |
| ; AVX512-NEXT: retq |
| %z = call <32 x i16> @llvm.usub.sat.v32i16(<32 x i16> %x, <32 x i16> %y) |
| ret <32 x i16> %z |
| } |
| |
| ; Too narrow vectors, legalized by widening. |
| |
| define void @v8i8(<8 x i8>* %px, <8 x i8>* %py, <8 x i8>* %pz) nounwind { |
| ; SSE-LABEL: v8i8: |
| ; SSE: # %bb.0: |
| ; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero |
| ; SSE-NEXT: movq {{.*#+}} xmm1 = mem[0],zero |
| ; SSE-NEXT: psubusb %xmm1, %xmm0 |
| ; SSE-NEXT: movq %xmm0, (%rdx) |
| ; SSE-NEXT: retq |
| ; |
| ; AVX1-LABEL: v8i8: |
| ; AVX1: # %bb.0: |
| ; AVX1-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero |
| ; AVX1-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero |
| ; AVX1-NEXT: vpsubusb %xmm1, %xmm0, %xmm0 |
| ; AVX1-NEXT: vmovq %xmm0, (%rdx) |
| ; AVX1-NEXT: retq |
| ; |
| ; AVX2-LABEL: v8i8: |
| ; AVX2: # %bb.0: |
| ; AVX2-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero |
| ; AVX2-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero |
| ; AVX2-NEXT: vpsubusb %xmm1, %xmm0, %xmm0 |
| ; AVX2-NEXT: vmovq %xmm0, (%rdx) |
| ; AVX2-NEXT: retq |
| ; |
| ; AVX512-LABEL: v8i8: |
| ; AVX512: # %bb.0: |
| ; AVX512-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero |
| ; AVX512-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero |
| ; AVX512-NEXT: vpsubusb %xmm1, %xmm0, %xmm0 |
| ; AVX512-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero |
| ; AVX512-NEXT: vpmovwb %xmm0, (%rdx) |
| ; AVX512-NEXT: retq |
| %x = load <8 x i8>, <8 x i8>* %px |
| %y = load <8 x i8>, <8 x i8>* %py |
| %z = call <8 x i8> @llvm.usub.sat.v8i8(<8 x i8> %x, <8 x i8> %y) |
| store <8 x i8> %z, <8 x i8>* %pz |
| ret void |
| } |
| |
| define void @v4i8(<4 x i8>* %px, <4 x i8>* %py, <4 x i8>* %pz) nounwind { |
| ; SSE-LABEL: v4i8: |
| ; SSE: # %bb.0: |
| ; SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero |
| ; SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero |
| ; SSE-NEXT: psubusb %xmm1, %xmm0 |
| ; SSE-NEXT: movd %xmm0, (%rdx) |
| ; SSE-NEXT: retq |
| ; |
| ; AVX1-LABEL: v4i8: |
| ; AVX1: # %bb.0: |
| ; AVX1-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero |
| ; AVX1-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero |
| ; AVX1-NEXT: vpsubusb %xmm1, %xmm0, %xmm0 |
| ; AVX1-NEXT: vmovd %xmm0, (%rdx) |
| ; AVX1-NEXT: retq |
| ; |
| ; AVX2-LABEL: v4i8: |
| ; AVX2: # %bb.0: |
| ; AVX2-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero |
| ; AVX2-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero |
| ; AVX2-NEXT: vpsubusb %xmm1, %xmm0, %xmm0 |
| ; AVX2-NEXT: vmovd %xmm0, (%rdx) |
| ; AVX2-NEXT: retq |
| ; |
| ; AVX512-LABEL: v4i8: |
| ; AVX512: # %bb.0: |
| ; AVX512-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero |
| ; AVX512-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero |
| ; AVX512-NEXT: vpsubusb %xmm1, %xmm0, %xmm0 |
| ; AVX512-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero |
| ; AVX512-NEXT: vpmovdb %xmm0, (%rdx) |
| ; AVX512-NEXT: retq |
| %x = load <4 x i8>, <4 x i8>* %px |
| %y = load <4 x i8>, <4 x i8>* %py |
| %z = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> %x, <4 x i8> %y) |
| store <4 x i8> %z, <4 x i8>* %pz |
| ret void |
| } |
| |
| define void @v2i8(<2 x i8>* %px, <2 x i8>* %py, <2 x i8>* %pz) nounwind { |
| ; SSE2-LABEL: v2i8: |
| ; SSE2: # %bb.0: |
| ; SSE2-NEXT: movzwl (%rdi), %eax |
| ; SSE2-NEXT: movd %eax, %xmm0 |
| ; SSE2-NEXT: movzwl (%rsi), %eax |
| ; SSE2-NEXT: movd %eax, %xmm1 |
| ; SSE2-NEXT: psubusb %xmm1, %xmm0 |
| ; SSE2-NEXT: movd %xmm0, %eax |
| ; SSE2-NEXT: movw %ax, (%rdx) |
| ; SSE2-NEXT: retq |
| ; |
| ; SSSE3-LABEL: v2i8: |
| ; SSSE3: # %bb.0: |
| ; SSSE3-NEXT: movzwl (%rdi), %eax |
| ; SSSE3-NEXT: movd %eax, %xmm0 |
| ; SSSE3-NEXT: movzwl (%rsi), %eax |
| ; SSSE3-NEXT: movd %eax, %xmm1 |
| ; SSSE3-NEXT: psubusb %xmm1, %xmm0 |
| ; SSSE3-NEXT: movd %xmm0, %eax |
| ; SSSE3-NEXT: movw %ax, (%rdx) |
| ; SSSE3-NEXT: retq |
| ; |
| ; SSE41-LABEL: v2i8: |
| ; SSE41: # %bb.0: |
| ; SSE41-NEXT: movzwl (%rdi), %eax |
| ; SSE41-NEXT: movd %eax, %xmm0 |
| ; SSE41-NEXT: movzwl (%rsi), %eax |
| ; SSE41-NEXT: movd %eax, %xmm1 |
| ; SSE41-NEXT: psubusb %xmm1, %xmm0 |
| ; SSE41-NEXT: pextrw $0, %xmm0, (%rdx) |
| ; SSE41-NEXT: retq |
| ; |
| ; AVX1-LABEL: v2i8: |
| ; AVX1: # %bb.0: |
| ; AVX1-NEXT: movzwl (%rdi), %eax |
| ; AVX1-NEXT: vmovd %eax, %xmm0 |
| ; AVX1-NEXT: movzwl (%rsi), %eax |
| ; AVX1-NEXT: vmovd %eax, %xmm1 |
| ; AVX1-NEXT: vpsubusb %xmm1, %xmm0, %xmm0 |
| ; AVX1-NEXT: vpextrw $0, %xmm0, (%rdx) |
| ; AVX1-NEXT: retq |
| ; |
| ; AVX2-LABEL: v2i8: |
| ; AVX2: # %bb.0: |
| ; AVX2-NEXT: movzwl (%rdi), %eax |
| ; AVX2-NEXT: vmovd %eax, %xmm0 |
| ; AVX2-NEXT: movzwl (%rsi), %eax |
| ; AVX2-NEXT: vmovd %eax, %xmm1 |
| ; AVX2-NEXT: vpsubusb %xmm1, %xmm0, %xmm0 |
| ; AVX2-NEXT: vpextrw $0, %xmm0, (%rdx) |
| ; AVX2-NEXT: retq |
| ; |
| ; AVX512-LABEL: v2i8: |
| ; AVX512: # %bb.0: |
| ; AVX512-NEXT: movzwl (%rdi), %eax |
| ; AVX512-NEXT: vmovd %eax, %xmm0 |
| ; AVX512-NEXT: movzwl (%rsi), %eax |
| ; AVX512-NEXT: vmovd %eax, %xmm1 |
| ; AVX512-NEXT: vpsubusb %xmm1, %xmm0, %xmm0 |
| ; AVX512-NEXT: vpmovzxbq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero |
| ; AVX512-NEXT: vpmovqb %xmm0, (%rdx) |
| ; AVX512-NEXT: retq |
| %x = load <2 x i8>, <2 x i8>* %px |
| %y = load <2 x i8>, <2 x i8>* %py |
| %z = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %x, <2 x i8> %y) |
| store <2 x i8> %z, <2 x i8>* %pz |
| ret void |
| } |
| |
| define void @v4i16(<4 x i16>* %px, <4 x i16>* %py, <4 x i16>* %pz) nounwind { |
| ; SSE-LABEL: v4i16: |
| ; SSE: # %bb.0: |
| ; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero |
| ; SSE-NEXT: movq {{.*#+}} xmm1 = mem[0],zero |
| ; SSE-NEXT: psubusw %xmm1, %xmm0 |
| ; SSE-NEXT: movq %xmm0, (%rdx) |
| ; SSE-NEXT: retq |
| ; |
| ; AVX1-LABEL: v4i16: |
| ; AVX1: # %bb.0: |
| ; AVX1-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero |
| ; AVX1-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero |
| ; AVX1-NEXT: vpsubusw %xmm1, %xmm0, %xmm0 |
| ; AVX1-NEXT: vmovq %xmm0, (%rdx) |
| ; AVX1-NEXT: retq |
| ; |
| ; AVX2-LABEL: v4i16: |
| ; AVX2: # %bb.0: |
| ; AVX2-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero |
| ; AVX2-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero |
| ; AVX2-NEXT: vpsubusw %xmm1, %xmm0, %xmm0 |
| ; AVX2-NEXT: vmovq %xmm0, (%rdx) |
| ; AVX2-NEXT: retq |
| ; |
| ; AVX512-LABEL: v4i16: |
| ; AVX512: # %bb.0: |
| ; AVX512-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero |
| ; AVX512-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero |
| ; AVX512-NEXT: vpsubusw %xmm1, %xmm0, %xmm0 |
| ; AVX512-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero |
| ; AVX512-NEXT: vpmovdw %xmm0, (%rdx) |
| ; AVX512-NEXT: retq |
| %x = load <4 x i16>, <4 x i16>* %px |
| %y = load <4 x i16>, <4 x i16>* %py |
| %z = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> %x, <4 x i16> %y) |
| store <4 x i16> %z, <4 x i16>* %pz |
| ret void |
| } |
| |
| define void @v2i16(<2 x i16>* %px, <2 x i16>* %py, <2 x i16>* %pz) nounwind { |
| ; SSE-LABEL: v2i16: |
| ; SSE: # %bb.0: |
| ; SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero |
| ; SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero |
| ; SSE-NEXT: psubusw %xmm1, %xmm0 |
| ; SSE-NEXT: movd %xmm0, (%rdx) |
| ; SSE-NEXT: retq |
| ; |
| ; AVX1-LABEL: v2i16: |
| ; AVX1: # %bb.0: |
| ; AVX1-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero |
| ; AVX1-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero |
| ; AVX1-NEXT: vpsubusw %xmm1, %xmm0, %xmm0 |
| ; AVX1-NEXT: vmovd %xmm0, (%rdx) |
| ; AVX1-NEXT: retq |
| ; |
| ; AVX2-LABEL: v2i16: |
| ; AVX2: # %bb.0: |
| ; AVX2-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero |
| ; AVX2-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero |
| ; AVX2-NEXT: vpsubusw %xmm1, %xmm0, %xmm0 |
| ; AVX2-NEXT: vmovd %xmm0, (%rdx) |
| ; AVX2-NEXT: retq |
| ; |
| ; AVX512-LABEL: v2i16: |
| ; AVX512: # %bb.0: |
| ; AVX512-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero |
| ; AVX512-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero |
| ; AVX512-NEXT: vpsubusw %xmm1, %xmm0, %xmm0 |
| ; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero |
| ; AVX512-NEXT: vpmovqw %xmm0, (%rdx) |
| ; AVX512-NEXT: retq |
| %x = load <2 x i16>, <2 x i16>* %px |
| %y = load <2 x i16>, <2 x i16>* %py |
| %z = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %x, <2 x i16> %y) |
| store <2 x i16> %z, <2 x i16>* %pz |
| ret void |
| } |
| |
| define <12 x i8> @v12i8(<12 x i8> %x, <12 x i8> %y) nounwind { |
| ; SSE-LABEL: v12i8: |
| ; SSE: # %bb.0: |
| ; SSE-NEXT: psubusb %xmm1, %xmm0 |
| ; SSE-NEXT: retq |
| ; |
| ; AVX-LABEL: v12i8: |
| ; AVX: # %bb.0: |
| ; AVX-NEXT: vpsubusb %xmm1, %xmm0, %xmm0 |
| ; AVX-NEXT: retq |
| %z = call <12 x i8> @llvm.usub.sat.v12i8(<12 x i8> %x, <12 x i8> %y) |
| ret <12 x i8> %z |
| } |
| |
| define void @v12i16(<12 x i16>* %px, <12 x i16>* %py, <12 x i16>* %pz) nounwind { |
| ; SSE-LABEL: v12i16: |
| ; SSE: # %bb.0: |
| ; SSE-NEXT: movdqa (%rdi), %xmm0 |
| ; SSE-NEXT: movdqa 16(%rdi), %xmm1 |
| ; SSE-NEXT: psubusw (%rsi), %xmm0 |
| ; SSE-NEXT: psubusw 16(%rsi), %xmm1 |
| ; SSE-NEXT: movq %xmm1, 16(%rdx) |
| ; SSE-NEXT: movdqa %xmm0, (%rdx) |
| ; SSE-NEXT: retq |
| ; |
| ; AVX1-LABEL: v12i16: |
| ; AVX1: # %bb.0: |
| ; AVX1-NEXT: vmovdqa (%rdi), %xmm0 |
| ; AVX1-NEXT: vmovdqa 16(%rdi), %xmm1 |
| ; AVX1-NEXT: vpsubusw (%rsi), %xmm0, %xmm0 |
| ; AVX1-NEXT: vpsubusw 16(%rsi), %xmm1, %xmm1 |
| ; AVX1-NEXT: vmovq %xmm1, 16(%rdx) |
| ; AVX1-NEXT: vmovdqa %xmm0, (%rdx) |
| ; AVX1-NEXT: retq |
| ; |
| ; AVX2-LABEL: v12i16: |
| ; AVX2: # %bb.0: |
| ; AVX2-NEXT: vmovdqa (%rdi), %ymm0 |
| ; AVX2-NEXT: vpsubusw (%rsi), %ymm0, %ymm0 |
| ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 |
| ; AVX2-NEXT: vmovq %xmm1, 16(%rdx) |
| ; AVX2-NEXT: vmovdqa %xmm0, (%rdx) |
| ; AVX2-NEXT: vzeroupper |
| ; AVX2-NEXT: retq |
| ; |
| ; AVX512-LABEL: v12i16: |
| ; AVX512: # %bb.0: |
| ; AVX512-NEXT: vmovdqa (%rdi), %ymm0 |
| ; AVX512-NEXT: vpsubusw (%rsi), %ymm0, %ymm0 |
| ; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1 |
| ; AVX512-NEXT: vmovq %xmm1, 16(%rdx) |
| ; AVX512-NEXT: vmovdqa %xmm0, (%rdx) |
| ; AVX512-NEXT: vzeroupper |
| ; AVX512-NEXT: retq |
| %x = load <12 x i16>, <12 x i16>* %px |
| %y = load <12 x i16>, <12 x i16>* %py |
| %z = call <12 x i16> @llvm.usub.sat.v12i16(<12 x i16> %x, <12 x i16> %y) |
| store <12 x i16> %z, <12 x i16>* %pz |
| ret void |
| } |
| |
| ; Scalarization |
| |
| define void @v1i8(<1 x i8>* %px, <1 x i8>* %py, <1 x i8>* %pz) nounwind { |
| ; SSE-LABEL: v1i8: |
| ; SSE: # %bb.0: |
| ; SSE-NEXT: movb (%rdi), %al |
| ; SSE-NEXT: subb (%rsi), %al |
| ; SSE-NEXT: jae .LBB13_2 |
| ; SSE-NEXT: # %bb.1: |
| ; SSE-NEXT: xorl %eax, %eax |
| ; SSE-NEXT: .LBB13_2: |
| ; SSE-NEXT: movb %al, (%rdx) |
| ; SSE-NEXT: retq |
| ; |
| ; AVX-LABEL: v1i8: |
| ; AVX: # %bb.0: |
| ; AVX-NEXT: movb (%rdi), %al |
| ; AVX-NEXT: subb (%rsi), %al |
| ; AVX-NEXT: jae .LBB13_2 |
| ; AVX-NEXT: # %bb.1: |
| ; AVX-NEXT: xorl %eax, %eax |
| ; AVX-NEXT: .LBB13_2: |
| ; AVX-NEXT: movb %al, (%rdx) |
| ; AVX-NEXT: retq |
| %x = load <1 x i8>, <1 x i8>* %px |
| %y = load <1 x i8>, <1 x i8>* %py |
| %z = call <1 x i8> @llvm.usub.sat.v1i8(<1 x i8> %x, <1 x i8> %y) |
| store <1 x i8> %z, <1 x i8>* %pz |
| ret void |
| } |
| |
| define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind { |
| ; SSE-LABEL: v1i16: |
| ; SSE: # %bb.0: |
| ; SSE-NEXT: movzwl (%rdi), %eax |
| ; SSE-NEXT: xorl %ecx, %ecx |
| ; SSE-NEXT: subw (%rsi), %ax |
| ; SSE-NEXT: cmovbl %ecx, %eax |
| ; SSE-NEXT: movw %ax, (%rdx) |
| ; SSE-NEXT: retq |
| ; |
| ; AVX-LABEL: v1i16: |
| ; AVX: # %bb.0: |
| ; AVX-NEXT: movzwl (%rdi), %eax |
| ; AVX-NEXT: xorl %ecx, %ecx |
| ; AVX-NEXT: subw (%rsi), %ax |
| ; AVX-NEXT: cmovbl %ecx, %eax |
| ; AVX-NEXT: movw %ax, (%rdx) |
| ; AVX-NEXT: retq |
| %x = load <1 x i16>, <1 x i16>* %px |
| %y = load <1 x i16>, <1 x i16>* %py |
| %z = call <1 x i16> @llvm.usub.sat.v1i16(<1 x i16> %x, <1 x i16> %y) |
| store <1 x i16> %z, <1 x i16>* %pz |
| ret void |
| } |
| |
| ; Promotion |
| |
| define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind { |
| ; SSE-LABEL: v16i4: |
| ; SSE: # %bb.0: |
| ; SSE-NEXT: psllw $4, %xmm1 |
| ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] |
| ; SSE-NEXT: pand %xmm2, %xmm1 |
| ; SSE-NEXT: psllw $4, %xmm0 |
| ; SSE-NEXT: pand %xmm2, %xmm0 |
| ; SSE-NEXT: psubusb %xmm1, %xmm0 |
| ; SSE-NEXT: psrlw $4, %xmm0 |
| ; SSE-NEXT: pand {{.*}}(%rip), %xmm0 |
| ; SSE-NEXT: retq |
| ; |
| ; AVX-LABEL: v16i4: |
| ; AVX: # %bb.0: |
| ; AVX-NEXT: vpsllw $4, %xmm1, %xmm1 |
| ; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240] |
| ; AVX-NEXT: vpand %xmm2, %xmm1, %xmm1 |
| ; AVX-NEXT: vpsllw $4, %xmm0, %xmm0 |
| ; AVX-NEXT: vpand %xmm2, %xmm0, %xmm0 |
| ; AVX-NEXT: vpsubusb %xmm1, %xmm0, %xmm0 |
| ; AVX-NEXT: vpsrlw $4, %xmm0, %xmm0 |
| ; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 |
| ; AVX-NEXT: retq |
| %z = call <16 x i4> @llvm.usub.sat.v16i4(<16 x i4> %x, <16 x i4> %y) |
| ret <16 x i4> %z |
| } |
| |
| define <16 x i1> @v16i1(<16 x i1> %x, <16 x i1> %y) nounwind { |
| ; SSE-LABEL: v16i1: |
| ; SSE: # %bb.0: |
| ; SSE-NEXT: psllw $7, %xmm1 |
| ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128] |
| ; SSE-NEXT: pand %xmm2, %xmm1 |
| ; SSE-NEXT: psllw $7, %xmm0 |
| ; SSE-NEXT: pand %xmm2, %xmm0 |
| ; SSE-NEXT: psubusb %xmm1, %xmm0 |
| ; SSE-NEXT: psrlw $7, %xmm0 |
| ; SSE-NEXT: pand {{.*}}(%rip), %xmm0 |
| ; SSE-NEXT: retq |
| ; |
| ; AVX1-LABEL: v16i1: |
| ; AVX1: # %bb.0: |
| ; AVX1-NEXT: vpsllw $7, %xmm1, %xmm1 |
| ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128] |
| ; AVX1-NEXT: vpand %xmm2, %xmm1, %xmm1 |
| ; AVX1-NEXT: vpsllw $7, %xmm0, %xmm0 |
| ; AVX1-NEXT: vpand %xmm2, %xmm0, %xmm0 |
| ; AVX1-NEXT: vpsubusb %xmm1, %xmm0, %xmm0 |
| ; AVX1-NEXT: vpsrlw $7, %xmm0, %xmm0 |
| ; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 |
| ; AVX1-NEXT: retq |
| ; |
| ; AVX2-LABEL: v16i1: |
| ; AVX2: # %bb.0: |
| ; AVX2-NEXT: vpsllw $7, %xmm1, %xmm1 |
| ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128] |
| ; AVX2-NEXT: vpand %xmm2, %xmm1, %xmm1 |
| ; AVX2-NEXT: vpsllw $7, %xmm0, %xmm0 |
| ; AVX2-NEXT: vpand %xmm2, %xmm0, %xmm0 |
| ; AVX2-NEXT: vpsubusb %xmm1, %xmm0, %xmm0 |
| ; AVX2-NEXT: vpsrlw $7, %xmm0, %xmm0 |
| ; AVX2-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 |
| ; AVX2-NEXT: retq |
| ; |
| ; AVX512-LABEL: v16i1: |
| ; AVX512: # %bb.0: |
| ; AVX512-NEXT: vpsllw $7, %xmm0, %xmm0 |
| ; AVX512-NEXT: vpmovb2m %xmm0, %k0 |
| ; AVX512-NEXT: vpsllw $7, %xmm1, %xmm0 |
| ; AVX512-NEXT: vpmovb2m %xmm0, %k1 |
| ; AVX512-NEXT: kandnw %k0, %k1, %k0 |
| ; AVX512-NEXT: vpmovm2b %k0, %xmm0 |
| ; AVX512-NEXT: retq |
| %z = call <16 x i1> @llvm.usub.sat.v16i1(<16 x i1> %x, <16 x i1> %y) |
| ret <16 x i1> %z |
| } |
| |
| ; Expanded |
| |
| define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind { |
| ; SSE2-LABEL: v4i32: |
| ; SSE2: # %bb.0: |
| ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[3,1,2,3] |
| ; SSE2-NEXT: movd %xmm2, %eax |
| ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[3,1,2,3] |
| ; SSE2-NEXT: movd %xmm2, %ecx |
| ; SSE2-NEXT: xorl %edx, %edx |
| ; SSE2-NEXT: subl %eax, %ecx |
| ; SSE2-NEXT: cmovbl %edx, %ecx |
| ; SSE2-NEXT: movd %ecx, %xmm2 |
| ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1] |
| ; SSE2-NEXT: movd %xmm3, %eax |
| ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,0,1] |
| ; SSE2-NEXT: movd %xmm3, %ecx |
| ; SSE2-NEXT: subl %eax, %ecx |
| ; SSE2-NEXT: cmovbl %edx, %ecx |
| ; SSE2-NEXT: movd %ecx, %xmm3 |
| ; SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1] |
| ; SSE2-NEXT: movd %xmm1, %eax |
| ; SSE2-NEXT: movd %xmm0, %ecx |
| ; SSE2-NEXT: subl %eax, %ecx |
| ; SSE2-NEXT: cmovbl %edx, %ecx |
| ; SSE2-NEXT: movd %ecx, %xmm2 |
| ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,2,3] |
| ; SSE2-NEXT: movd %xmm1, %eax |
| ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3] |
| ; SSE2-NEXT: movd %xmm0, %ecx |
| ; SSE2-NEXT: subl %eax, %ecx |
| ; SSE2-NEXT: cmovbl %edx, %ecx |
| ; SSE2-NEXT: movd %ecx, %xmm0 |
| ; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1] |
| ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0] |
| ; SSE2-NEXT: movdqa %xmm2, %xmm0 |
| ; SSE2-NEXT: retq |
| ; |
| ; SSSE3-LABEL: v4i32: |
| ; SSSE3: # %bb.0: |
| ; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm1[3,1,2,3] |
| ; SSSE3-NEXT: movd %xmm2, %eax |
| ; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm0[3,1,2,3] |
| ; SSSE3-NEXT: movd %xmm2, %ecx |
| ; SSSE3-NEXT: xorl %edx, %edx |
| ; SSSE3-NEXT: subl %eax, %ecx |
| ; SSSE3-NEXT: cmovbl %edx, %ecx |
| ; SSSE3-NEXT: movd %ecx, %xmm2 |
| ; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1] |
| ; SSSE3-NEXT: movd %xmm3, %eax |
| ; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,0,1] |
| ; SSSE3-NEXT: movd %xmm3, %ecx |
| ; SSSE3-NEXT: subl %eax, %ecx |
| ; SSSE3-NEXT: cmovbl %edx, %ecx |
| ; SSSE3-NEXT: movd %ecx, %xmm3 |
| ; SSSE3-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1] |
| ; SSSE3-NEXT: movd %xmm1, %eax |
| ; SSSE3-NEXT: movd %xmm0, %ecx |
| ; SSSE3-NEXT: subl %eax, %ecx |
| ; SSSE3-NEXT: cmovbl %edx, %ecx |
| ; SSSE3-NEXT: movd %ecx, %xmm2 |
| ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,2,3] |
| ; SSSE3-NEXT: movd %xmm1, %eax |
| ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3] |
| ; SSSE3-NEXT: movd %xmm0, %ecx |
| ; SSSE3-NEXT: subl %eax, %ecx |
| ; SSSE3-NEXT: cmovbl %edx, %ecx |
| ; SSSE3-NEXT: movd %ecx, %xmm0 |
| ; SSSE3-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1] |
| ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0] |
| ; SSSE3-NEXT: movdqa %xmm2, %xmm0 |
| ; SSSE3-NEXT: retq |
| ; |
| ; SSE41-LABEL: v4i32: |
| ; SSE41: # %bb.0: |
| ; SSE41-NEXT: pextrd $1, %xmm1, %eax |
| ; SSE41-NEXT: pextrd $1, %xmm0, %ecx |
| ; SSE41-NEXT: xorl %edx, %edx |
| ; SSE41-NEXT: subl %eax, %ecx |
| ; SSE41-NEXT: cmovbl %edx, %ecx |
| ; SSE41-NEXT: movd %xmm1, %eax |
| ; SSE41-NEXT: movd %xmm0, %esi |
| ; SSE41-NEXT: subl %eax, %esi |
| ; SSE41-NEXT: cmovbl %edx, %esi |
| ; SSE41-NEXT: movd %esi, %xmm2 |
| ; SSE41-NEXT: pinsrd $1, %ecx, %xmm2 |
| ; SSE41-NEXT: pextrd $2, %xmm1, %eax |
| ; SSE41-NEXT: pextrd $2, %xmm0, %ecx |
| ; SSE41-NEXT: subl %eax, %ecx |
| ; SSE41-NEXT: cmovbl %edx, %ecx |
| ; SSE41-NEXT: pinsrd $2, %ecx, %xmm2 |
| ; SSE41-NEXT: pextrd $3, %xmm1, %eax |
| ; SSE41-NEXT: pextrd $3, %xmm0, %ecx |
| ; SSE41-NEXT: subl %eax, %ecx |
| ; SSE41-NEXT: cmovbl %edx, %ecx |
| ; SSE41-NEXT: pinsrd $3, %ecx, %xmm2 |
| ; SSE41-NEXT: movdqa %xmm2, %xmm0 |
| ; SSE41-NEXT: retq |
| ; |
| ; AVX-LABEL: v4i32: |
| ; AVX: # %bb.0: |
| ; AVX-NEXT: vpextrd $1, %xmm1, %eax |
| ; AVX-NEXT: vpextrd $1, %xmm0, %ecx |
| ; AVX-NEXT: xorl %edx, %edx |
| ; AVX-NEXT: subl %eax, %ecx |
| ; AVX-NEXT: cmovbl %edx, %ecx |
| ; AVX-NEXT: vmovd %xmm1, %eax |
| ; AVX-NEXT: vmovd %xmm0, %esi |
| ; AVX-NEXT: subl %eax, %esi |
| ; AVX-NEXT: cmovbl %edx, %esi |
| ; AVX-NEXT: vmovd %esi, %xmm2 |
| ; AVX-NEXT: vpinsrd $1, %ecx, %xmm2, %xmm2 |
| ; AVX-NEXT: vpextrd $2, %xmm1, %eax |
| ; AVX-NEXT: vpextrd $2, %xmm0, %ecx |
| ; AVX-NEXT: subl %eax, %ecx |
| ; AVX-NEXT: cmovbl %edx, %ecx |
| ; AVX-NEXT: vpinsrd $2, %ecx, %xmm2, %xmm2 |
| ; AVX-NEXT: vpextrd $3, %xmm1, %eax |
| ; AVX-NEXT: vpextrd $3, %xmm0, %ecx |
| ; AVX-NEXT: subl %eax, %ecx |
| ; AVX-NEXT: cmovbl %edx, %ecx |
| ; AVX-NEXT: vpinsrd $3, %ecx, %xmm2, %xmm0 |
| ; AVX-NEXT: retq |
| %z = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %x, <4 x i32> %y) |
| ret <4 x i32> %z |
| } |
| |
| define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind { |
| ; SSE2-LABEL: v2i32: |
| ; SSE2: # %bb.0: |
| ; SSE2-NEXT: psllq $32, %xmm1 |
| ; SSE2-NEXT: movq %xmm1, %rax |
| ; SSE2-NEXT: psllq $32, %xmm0 |
| ; SSE2-NEXT: movq %xmm0, %rcx |
| ; SSE2-NEXT: xorl %edx, %edx |
| ; SSE2-NEXT: subq %rax, %rcx |
| ; SSE2-NEXT: cmovbq %rdx, %rcx |
| ; SSE2-NEXT: movq %rcx, %xmm2 |
| ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] |
| ; SSE2-NEXT: movq %xmm1, %rax |
| ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] |
| ; SSE2-NEXT: movq %xmm0, %rcx |
| ; SSE2-NEXT: subq %rax, %rcx |
| ; SSE2-NEXT: cmovbq %rdx, %rcx |
| ; SSE2-NEXT: movq %rcx, %xmm0 |
| ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0] |
| ; SSE2-NEXT: psrlq $32, %xmm2 |
| ; SSE2-NEXT: movdqa %xmm2, %xmm0 |
| ; SSE2-NEXT: retq |
| ; |
| ; SSSE3-LABEL: v2i32: |
| ; SSSE3: # %bb.0: |
| ; SSSE3-NEXT: psllq $32, %xmm1 |
| ; SSSE3-NEXT: movq %xmm1, %rax |
| ; SSSE3-NEXT: psllq $32, %xmm0 |
| ; SSSE3-NEXT: movq %xmm0, %rcx |
| ; SSSE3-NEXT: xorl %edx, %edx |
| ; SSSE3-NEXT: subq %rax, %rcx |
| ; SSSE3-NEXT: cmovbq %rdx, %rcx |
| ; SSSE3-NEXT: movq %rcx, %xmm2 |
| ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] |
| ; SSSE3-NEXT: movq %xmm1, %rax |
| ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] |
| ; SSSE3-NEXT: movq %xmm0, %rcx |
| ; SSSE3-NEXT: subq %rax, %rcx |
| ; SSSE3-NEXT: cmovbq %rdx, %rcx |
| ; SSSE3-NEXT: movq %rcx, %xmm0 |
| ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0] |
| ; SSSE3-NEXT: psrlq $32, %xmm2 |
| ; SSSE3-NEXT: movdqa %xmm2, %xmm0 |
| ; SSSE3-NEXT: retq |
| ; |
| ; SSE41-LABEL: v2i32: |
| ; SSE41: # %bb.0: |
| ; SSE41-NEXT: psllq $32, %xmm1 |
| ; SSE41-NEXT: pextrq $1, %xmm1, %rax |
| ; SSE41-NEXT: psllq $32, %xmm0 |
| ; SSE41-NEXT: pextrq $1, %xmm0, %rcx |
| ; SSE41-NEXT: xorl %edx, %edx |
| ; SSE41-NEXT: subq %rax, %rcx |
| ; SSE41-NEXT: cmovbq %rdx, %rcx |
| ; SSE41-NEXT: movq %rcx, %xmm2 |
| ; SSE41-NEXT: movq %xmm1, %rax |
| ; SSE41-NEXT: movq %xmm0, %rcx |
| ; SSE41-NEXT: subq %rax, %rcx |
| ; SSE41-NEXT: cmovbq %rdx, %rcx |
| ; SSE41-NEXT: movq %rcx, %xmm0 |
| ; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] |
| ; SSE41-NEXT: psrlq $32, %xmm0 |
| ; SSE41-NEXT: retq |
| ; |
| ; AVX-LABEL: v2i32: |
| ; AVX: # %bb.0: |
| ; AVX-NEXT: vpsllq $32, %xmm1, %xmm1 |
| ; AVX-NEXT: vpextrq $1, %xmm1, %rax |
| ; AVX-NEXT: vpsllq $32, %xmm0, %xmm0 |
| ; AVX-NEXT: vpextrq $1, %xmm0, %rcx |
| ; AVX-NEXT: xorl %edx, %edx |
| ; AVX-NEXT: subq %rax, %rcx |
| ; AVX-NEXT: cmovbq %rdx, %rcx |
| ; AVX-NEXT: vmovq %rcx, %xmm2 |
| ; AVX-NEXT: vmovq %xmm1, %rax |
| ; AVX-NEXT: vmovq %xmm0, %rcx |
| ; AVX-NEXT: subq %rax, %rcx |
| ; AVX-NEXT: cmovbq %rdx, %rcx |
| ; AVX-NEXT: vmovq %rcx, %xmm0 |
| ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] |
| ; AVX-NEXT: vpsrlq $32, %xmm0, %xmm0 |
| ; AVX-NEXT: retq |
| %z = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %x, <2 x i32> %y) |
| ret <2 x i32> %z |
| } |
| |
| define <4 x i24> @v4i24(<4 x i24> %x, <4 x i24> %y) nounwind { |
| ; SSE2-LABEL: v4i24: |
| ; SSE2: # %bb.0: |
| ; SSE2-NEXT: pslld $8, %xmm1 |
| ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[3,1,2,3] |
| ; SSE2-NEXT: movd %xmm2, %eax |
| ; SSE2-NEXT: pslld $8, %xmm0 |
| ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[3,1,2,3] |
| ; SSE2-NEXT: movd %xmm2, %ecx |
| ; SSE2-NEXT: xorl %edx, %edx |
| ; SSE2-NEXT: subl %eax, %ecx |
| ; SSE2-NEXT: cmovbl %edx, %ecx |
| ; SSE2-NEXT: movd %ecx, %xmm2 |
| ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1] |
| ; SSE2-NEXT: movd %xmm3, %eax |
| ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,0,1] |
| ; SSE2-NEXT: movd %xmm3, %ecx |
| ; SSE2-NEXT: subl %eax, %ecx |
| ; SSE2-NEXT: cmovbl %edx, %ecx |
| ; SSE2-NEXT: movd %ecx, %xmm3 |
| ; SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1] |
| ; SSE2-NEXT: movd %xmm1, %eax |
| ; SSE2-NEXT: movd %xmm0, %ecx |
| ; SSE2-NEXT: subl %eax, %ecx |
| ; SSE2-NEXT: cmovbl %edx, %ecx |
| ; SSE2-NEXT: movd %ecx, %xmm2 |
| ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,2,3] |
| ; SSE2-NEXT: movd %xmm1, %eax |
| ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3] |
| ; SSE2-NEXT: movd %xmm0, %ecx |
| ; SSE2-NEXT: subl %eax, %ecx |
| ; SSE2-NEXT: cmovbl %edx, %ecx |
| ; SSE2-NEXT: movd %ecx, %xmm0 |
| ; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1] |
| ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0] |
| ; SSE2-NEXT: psrld $8, %xmm2 |
| ; SSE2-NEXT: movdqa %xmm2, %xmm0 |
| ; SSE2-NEXT: retq |
| ; |
| ; SSSE3-LABEL: v4i24: |
| ; SSSE3: # %bb.0: |
| ; SSSE3-NEXT: pslld $8, %xmm1 |
| ; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm1[3,1,2,3] |
| ; SSSE3-NEXT: movd %xmm2, %eax |
| ; SSSE3-NEXT: pslld $8, %xmm0 |
| ; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm0[3,1,2,3] |
| ; SSSE3-NEXT: movd %xmm2, %ecx |
| ; SSSE3-NEXT: xorl %edx, %edx |
| ; SSSE3-NEXT: subl %eax, %ecx |
| ; SSSE3-NEXT: cmovbl %edx, %ecx |
| ; SSSE3-NEXT: movd %ecx, %xmm2 |
| ; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1] |
| ; SSSE3-NEXT: movd %xmm3, %eax |
| ; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,0,1] |
| ; SSSE3-NEXT: movd %xmm3, %ecx |
| ; SSSE3-NEXT: subl %eax, %ecx |
| ; SSSE3-NEXT: cmovbl %edx, %ecx |
| ; SSSE3-NEXT: movd %ecx, %xmm3 |
| ; SSSE3-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1] |
| ; SSSE3-NEXT: movd %xmm1, %eax |
| ; SSSE3-NEXT: movd %xmm0, %ecx |
| ; SSSE3-NEXT: subl %eax, %ecx |
| ; SSSE3-NEXT: cmovbl %edx, %ecx |
| ; SSSE3-NEXT: movd %ecx, %xmm2 |
| ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,2,3] |
| ; SSSE3-NEXT: movd %xmm1, %eax |
| ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3] |
| ; SSSE3-NEXT: movd %xmm0, %ecx |
| ; SSSE3-NEXT: subl %eax, %ecx |
| ; SSSE3-NEXT: cmovbl %edx, %ecx |
| ; SSSE3-NEXT: movd %ecx, %xmm0 |
| ; SSSE3-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1] |
| ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0] |
| ; SSSE3-NEXT: psrld $8, %xmm2 |
| ; SSSE3-NEXT: movdqa %xmm2, %xmm0 |
| ; SSSE3-NEXT: retq |
| ; |
| ; SSE41-LABEL: v4i24: |
| ; SSE41: # %bb.0: |
| ; SSE41-NEXT: pslld $8, %xmm1 |
| ; SSE41-NEXT: pextrd $1, %xmm1, %eax |
| ; SSE41-NEXT: pslld $8, %xmm0 |
| ; SSE41-NEXT: pextrd $1, %xmm0, %ecx |
| ; SSE41-NEXT: xorl %edx, %edx |
| ; SSE41-NEXT: subl %eax, %ecx |
| ; SSE41-NEXT: cmovbl %edx, %ecx |
| ; SSE41-NEXT: movd %xmm1, %eax |
| ; SSE41-NEXT: movd %xmm0, %esi |
| ; SSE41-NEXT: subl %eax, %esi |
| ; SSE41-NEXT: cmovbl %edx, %esi |
| ; SSE41-NEXT: movd %esi, %xmm2 |
| ; SSE41-NEXT: pinsrd $1, %ecx, %xmm2 |
| ; SSE41-NEXT: pextrd $2, %xmm1, %eax |
| ; SSE41-NEXT: pextrd $2, %xmm0, %ecx |
| ; SSE41-NEXT: subl %eax, %ecx |
| ; SSE41-NEXT: cmovbl %edx, %ecx |
| ; SSE41-NEXT: pinsrd $2, %ecx, %xmm2 |
| ; SSE41-NEXT: pextrd $3, %xmm1, %eax |
| ; SSE41-NEXT: pextrd $3, %xmm0, %ecx |
| ; SSE41-NEXT: subl %eax, %ecx |
| ; SSE41-NEXT: cmovbl %edx, %ecx |
| ; SSE41-NEXT: pinsrd $3, %ecx, %xmm2 |
| ; SSE41-NEXT: psrld $8, %xmm2 |
| ; SSE41-NEXT: movdqa %xmm2, %xmm0 |
| ; SSE41-NEXT: retq |
| ; |
| ; AVX-LABEL: v4i24: |
| ; AVX: # %bb.0: |
| ; AVX-NEXT: vpslld $8, %xmm1, %xmm1 |
| ; AVX-NEXT: vpextrd $1, %xmm1, %eax |
| ; AVX-NEXT: vpslld $8, %xmm0, %xmm0 |
| ; AVX-NEXT: vpextrd $1, %xmm0, %ecx |
| ; AVX-NEXT: xorl %edx, %edx |
| ; AVX-NEXT: subl %eax, %ecx |
| ; AVX-NEXT: cmovbl %edx, %ecx |
| ; AVX-NEXT: vmovd %xmm1, %eax |
| ; AVX-NEXT: vmovd %xmm0, %esi |
| ; AVX-NEXT: subl %eax, %esi |
| ; AVX-NEXT: cmovbl %edx, %esi |
| ; AVX-NEXT: vmovd %esi, %xmm2 |
| ; AVX-NEXT: vpinsrd $1, %ecx, %xmm2, %xmm2 |
| ; AVX-NEXT: vpextrd $2, %xmm1, %eax |
| ; AVX-NEXT: vpextrd $2, %xmm0, %ecx |
| ; AVX-NEXT: subl %eax, %ecx |
| ; AVX-NEXT: cmovbl %edx, %ecx |
| ; AVX-NEXT: vpinsrd $2, %ecx, %xmm2, %xmm2 |
| ; AVX-NEXT: vpextrd $3, %xmm1, %eax |
| ; AVX-NEXT: vpextrd $3, %xmm0, %ecx |
| ; AVX-NEXT: subl %eax, %ecx |
| ; AVX-NEXT: cmovbl %edx, %ecx |
| ; AVX-NEXT: vpinsrd $3, %ecx, %xmm2, %xmm0 |
| ; AVX-NEXT: vpsrld $8, %xmm0, %xmm0 |
| ; AVX-NEXT: retq |
| %z = call <4 x i24> @llvm.usub.sat.v4i24(<4 x i24> %x, <4 x i24> %y) |
| ret <4 x i24> %z |
| } |
| |
| define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind { |
| ; SSE-LABEL: v2i128: |
| ; SSE: # %bb.0: |
| ; SSE-NEXT: movq %rdi, %rax |
| ; SSE-NEXT: xorl %edi, %edi |
| ; SSE-NEXT: subq %r9, %rsi |
| ; SSE-NEXT: sbbq {{[0-9]+}}(%rsp), %rdx |
| ; SSE-NEXT: cmovbq %rdi, %rsi |
| ; SSE-NEXT: cmovbq %rdi, %rdx |
| ; SSE-NEXT: subq {{[0-9]+}}(%rsp), %rcx |
| ; SSE-NEXT: sbbq {{[0-9]+}}(%rsp), %r8 |
| ; SSE-NEXT: cmovbq %rdi, %r8 |
| ; SSE-NEXT: cmovbq %rdi, %rcx |
| ; SSE-NEXT: movq %r8, 24(%rax) |
| ; SSE-NEXT: movq %rcx, 16(%rax) |
| ; SSE-NEXT: movq %rdx, 8(%rax) |
| ; SSE-NEXT: movq %rsi, (%rax) |
| ; SSE-NEXT: retq |
| ; |
| ; AVX-LABEL: v2i128: |
| ; AVX: # %bb.0: |
| ; AVX-NEXT: movq %rdi, %rax |
| ; AVX-NEXT: xorl %edi, %edi |
| ; AVX-NEXT: subq %r9, %rsi |
| ; AVX-NEXT: sbbq {{[0-9]+}}(%rsp), %rdx |
| ; AVX-NEXT: cmovbq %rdi, %rsi |
| ; AVX-NEXT: cmovbq %rdi, %rdx |
| ; AVX-NEXT: subq {{[0-9]+}}(%rsp), %rcx |
| ; AVX-NEXT: sbbq {{[0-9]+}}(%rsp), %r8 |
| ; AVX-NEXT: cmovbq %rdi, %r8 |
| ; AVX-NEXT: cmovbq %rdi, %rcx |
| ; AVX-NEXT: movq %r8, 24(%rax) |
| ; AVX-NEXT: movq %rcx, 16(%rax) |
| ; AVX-NEXT: movq %rdx, 8(%rax) |
| ; AVX-NEXT: movq %rsi, (%rax) |
| ; AVX-NEXT: retq |
| %z = call <2 x i128> @llvm.usub.sat.v2i128(<2 x i128> %x, <2 x i128> %y) |
| ret <2 x i128> %z |
| } |