| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc < %s -mtriple=arm-eabi -mattr=+neon | FileCheck %s |
| |
| define <8 x i8> @vceqi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { |
| ; CHECK-LABEL: vceqi8: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r1] |
| ; CHECK-NEXT: vldr d17, [r0] |
| ; CHECK-NEXT: vceq.i8 d16, d17, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: mov pc, lr |
| %tmp1 = load <8 x i8>, <8 x i8>* %A |
| %tmp2 = load <8 x i8>, <8 x i8>* %B |
| %tmp3 = icmp eq <8 x i8> %tmp1, %tmp2 |
| %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> |
| ret <8 x i8> %tmp4 |
| } |
| |
| define <4 x i16> @vceqi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { |
| ; CHECK-LABEL: vceqi16: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r1] |
| ; CHECK-NEXT: vldr d17, [r0] |
| ; CHECK-NEXT: vceq.i16 d16, d17, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: mov pc, lr |
| %tmp1 = load <4 x i16>, <4 x i16>* %A |
| %tmp2 = load <4 x i16>, <4 x i16>* %B |
| %tmp3 = icmp eq <4 x i16> %tmp1, %tmp2 |
| %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> |
| ret <4 x i16> %tmp4 |
| } |
| |
| define <2 x i32> @vceqi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { |
| ; CHECK-LABEL: vceqi32: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r1] |
| ; CHECK-NEXT: vldr d17, [r0] |
| ; CHECK-NEXT: vceq.i32 d16, d17, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: mov pc, lr |
| %tmp1 = load <2 x i32>, <2 x i32>* %A |
| %tmp2 = load <2 x i32>, <2 x i32>* %B |
| %tmp3 = icmp eq <2 x i32> %tmp1, %tmp2 |
| %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> |
| ret <2 x i32> %tmp4 |
| } |
| |
| define <2 x i32> @vceqf32(<2 x float>* %A, <2 x float>* %B) nounwind { |
| ; CHECK-LABEL: vceqf32: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r1] |
| ; CHECK-NEXT: vldr d17, [r0] |
| ; CHECK-NEXT: vceq.f32 d16, d17, d16 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: mov pc, lr |
| %tmp1 = load <2 x float>, <2 x float>* %A |
| %tmp2 = load <2 x float>, <2 x float>* %B |
| %tmp3 = fcmp oeq <2 x float> %tmp1, %tmp2 |
| %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> |
| ret <2 x i32> %tmp4 |
| } |
| |
| define <16 x i8> @vceqQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { |
| ; CHECK-LABEL: vceqQi8: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] |
| ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] |
| ; CHECK-NEXT: vceq.i8 q8, q9, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: mov pc, lr |
| %tmp1 = load <16 x i8>, <16 x i8>* %A |
| %tmp2 = load <16 x i8>, <16 x i8>* %B |
| %tmp3 = icmp eq <16 x i8> %tmp1, %tmp2 |
| %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> |
| ret <16 x i8> %tmp4 |
| } |
| |
| define <8 x i16> @vceqQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { |
| ; CHECK-LABEL: vceqQi16: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] |
| ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] |
| ; CHECK-NEXT: vceq.i16 q8, q9, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: mov pc, lr |
| %tmp1 = load <8 x i16>, <8 x i16>* %A |
| %tmp2 = load <8 x i16>, <8 x i16>* %B |
| %tmp3 = icmp eq <8 x i16> %tmp1, %tmp2 |
| %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> |
| ret <8 x i16> %tmp4 |
| } |
| |
| define <4 x i32> @vceqQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { |
| ; CHECK-LABEL: vceqQi32: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] |
| ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] |
| ; CHECK-NEXT: vceq.i32 q8, q9, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: mov pc, lr |
| %tmp1 = load <4 x i32>, <4 x i32>* %A |
| %tmp2 = load <4 x i32>, <4 x i32>* %B |
| %tmp3 = icmp eq <4 x i32> %tmp1, %tmp2 |
| %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> |
| ret <4 x i32> %tmp4 |
| } |
| |
| define <4 x i32> @vceqQf32(<4 x float>* %A, <4 x float>* %B) nounwind { |
| ; CHECK-LABEL: vceqQf32: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vld1.64 {d16, d17}, [r1] |
| ; CHECK-NEXT: vld1.64 {d18, d19}, [r0] |
| ; CHECK-NEXT: vceq.f32 q8, q9, q8 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: vmov r2, r3, d17 |
| ; CHECK-NEXT: mov pc, lr |
| %tmp1 = load <4 x float>, <4 x float>* %A |
| %tmp2 = load <4 x float>, <4 x float>* %B |
| %tmp3 = fcmp oeq <4 x float> %tmp1, %tmp2 |
| %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> |
| ret <4 x i32> %tmp4 |
| } |
| |
| define <8 x i8> @vceqi8Z(<8 x i8>* %A) nounwind { |
| ; CHECK-LABEL: vceqi8Z: |
| ; CHECK: @ %bb.0: |
| ; CHECK-NEXT: vldr d16, [r0] |
| ; CHECK-NEXT: vceq.i8 d16, d16, #0 |
| ; CHECK-NEXT: vmov r0, r1, d16 |
| ; CHECK-NEXT: mov pc, lr |
| %tmp1 = load <8 x i8>, <8 x i8>* %A |
| %tmp3 = icmp eq <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0> |
| %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> |
| ret <8 x i8> %tmp4 |
| } |