[Thumb] Fix infinite loop in ABS expansion (PR41160)
Don't expand ISD::ABS node if its legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356661 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index be6d11a..36df387 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -10391,9 +10391,12 @@
SelectionDAG &DAG = DCI.DAG;
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
- if (!TLI.expandABS(N, res, DAG))
+ if (TLI.isOperationLegal(N->getOpcode(), N->getValueType(0)))
return SDValue();
+ if (!TLI.expandABS(N, res, DAG))
+ return SDValue();
+
return res;
}
diff --git a/test/CodeGen/Thumb/iabs-vector.ll b/test/CodeGen/Thumb/iabs-vector.ll
new file mode 100644
index 0000000..169400f
--- /dev/null
+++ b/test/CodeGen/Thumb/iabs-vector.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=thumbv7--- | FileCheck %s
+
+define void @PR41160(<8 x i32>* %p) nounwind {
+; CHECK-LABEL: PR41160:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld1.8 {d16, d17}, [r0]
+; CHECK-NEXT: vabs.s32 q8, q8
+; CHECK-NEXT: vst1.8 {d16, d17}, [r0]!
+; CHECK-NEXT: vld1.8 {d16, d17}, [r0]
+; CHECK-NEXT: vabs.s32 q8, q8
+; CHECK-NEXT: vst1.8 {d16, d17}, [r0]
+; CHECK-NEXT: bx lr
+ %tmp1 = load <8 x i32>, <8 x i32>* %p, align 1
+ %tmp2 = icmp slt <8 x i32> %tmp1, zeroinitializer
+ %tmp3 = sub nsw <8 x i32> zeroinitializer, %tmp1
+ %tmp4 = select <8 x i1> %tmp2, <8 x i32> %tmp3, <8 x i32> %tmp1
+ store <8 x i32> %tmp4, <8 x i32>* %p, align 1
+ ret void
+}
