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607faa54b2ea98f97171b0094e18cc10681b8fde
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test
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CodeGen
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ARM
/
ret_arg5.ll
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; RUN: llvm-as < %s | llc -march=arm
define
i32
@test
(
i32
%a1
,
i32
%a2
,
i32
%a3
,
i32
%a4
,
i32
%a5
)
{
ret
i32
%a5
}