commit 550155b08743b6cc8e80b37cadef03e888afc4d0
author Craig Topper <craig.topper@intel.com> Sat Jan 12 02:22:06 2019 +0000
committer Craig Topper <craig.topper@intel.com> Sat Jan 12 02:22:06 2019 +0000
tree d06f4b1b31676a7ce188e14bac0e68764cfcdfd7
parent 2162d5fc62d60439a4be4e70e6a42ae6b95ec2ed

[X86] Change some patterns that select MOVZX16rm8 to instead select MOVZX32rm8 and extract the subregister.

This should be a shorter encoding and is consistent with what we do for zext i8->i16

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350988 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86InstrCompiler.td

diff --git a/lib/Target/X86/X86InstrCompiler.td b/lib/Target/X86/X86InstrCompiler.td
index 703c517..394dca8 100644
--- a/lib/Target/X86/X86InstrCompiler.td
+++ b/lib/Target/X86/X86InstrCompiler.td
@@ -1276,7 +1276,8 @@
 // i1 stored in one byte in zero-extended form.
 // Upper bits cleanup should be executed before Store.
 def : Pat<(zextloadi8i1  addr:$src), (MOV8rm addr:$src)>;
-def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
+def : Pat<(zextloadi16i1 addr:$src),
+          (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
 def : Pat<(zextloadi64i1 addr:$src),
           (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
@@ -1287,9 +1288,11 @@
 // defined, avoiding partial-register updates.
 
 def : Pat<(extloadi8i1 addr:$src),   (MOV8rm      addr:$src)>;
-def : Pat<(extloadi16i1 addr:$src),  (MOVZX16rm8  addr:$src)>;
+def : Pat<(extloadi16i1 addr:$src),
+          (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
 def : Pat<(extloadi32i1 addr:$src),  (MOVZX32rm8  addr:$src)>;
-def : Pat<(extloadi16i8 addr:$src),  (MOVZX16rm8  addr:$src)>;
+def : Pat<(extloadi16i8 addr:$src),
+          (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
 def : Pat<(extloadi32i8 addr:$src),  (MOVZX32rm8  addr:$src)>;
 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;