[AMDGPU][MC][GFX8+][DISASSEMBLER] Corrected 1/2pi value for 64-bit operands
See bug 39332: https://bugs.llvm.org/show_bug.cgi?id=39332
Reviewers: artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D56794
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@351555 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/docs/AMDGPUOperandSyntax.rst b/docs/AMDGPUOperandSyntax.rst
index 51e477a..8713c72 100644
--- a/docs/AMDGPUOperandSyntax.rst
+++ b/docs/AMDGPUOperandSyntax.rst
@@ -523,22 +523,22 @@
:ref:`expected operand type<amdgpu_syn_instruction_type>`
as described :ref:`here<amdgpu_synid_fp_const_conv>`.
- ================================== ===================================================== ==================
- Value Note Availability
- ================================== ===================================================== ==================
- 0.0 The same as integer constant 0. All GPUs
- 0.5 Floating-point constant 0.5 All GPUs
- 1.0 Floating-point constant 1.0 All GPUs
- 2.0 Floating-point constant 2.0 All GPUs
- 4.0 Floating-point constant 4.0 All GPUs
- -0.5 Floating-point constant -0.5 All GPUs
- -1.0 Floating-point constant -1.0 All GPUs
- -2.0 Floating-point constant -2.0 All GPUs
- -4.0 Floating-point constant -4.0 All GPUs
- 0.1592 1.0/(2.0*pi). Use only for 16-bit operands. GFX8, GFX9
- 0.15915494 1.0/(2.0*pi). Use only for 16- and 32-bit operands. GFX8, GFX9
- 0.159154943091895317852646485335 1.0/(2.0*pi). GFX8, GFX9
- ================================== ===================================================== ==================
+ ===================== ===================================================== ==================
+ Value Note Availability
+ ===================== ===================================================== ==================
+ 0.0 The same as integer constant 0. All GPUs
+ 0.5 Floating-point constant 0.5 All GPUs
+ 1.0 Floating-point constant 1.0 All GPUs
+ 2.0 Floating-point constant 2.0 All GPUs
+ 4.0 Floating-point constant 4.0 All GPUs
+ -0.5 Floating-point constant -0.5 All GPUs
+ -1.0 Floating-point constant -1.0 All GPUs
+ -2.0 Floating-point constant -2.0 All GPUs
+ -4.0 Floating-point constant -4.0 All GPUs
+ 0.1592 1.0/(2.0*pi). Use only for 16-bit operands. GFX8, GFX9
+ 0.15915494 1.0/(2.0*pi). Use only for 16- and 32-bit operands. GFX8, GFX9
+ 0.15915494309189532 1.0/(2.0*pi). GFX8, GFX9
+ ===================== ===================================================== ==================
.. WARNING:: GFX7 does not support inline constants for *f16* operands.
diff --git a/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp b/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
index fab0f87..1ffc71f 100644
--- a/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
+++ b/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
@@ -491,7 +491,7 @@
O << "-4.0";
else if (Imm == 0x3fc45f306dc9c882 &&
STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
- O << "0.15915494";
+ O << "0.15915494309189532";
else {
assert(isUInt<32>(Imm) || Imm == 0x3fc45f306dc9c882);
diff --git a/test/CodeGen/AMDGPU/imm.ll b/test/CodeGen/AMDGPU/imm.ll
index bb9da71..2ef4c74 100644
--- a/test/CodeGen/AMDGPU/imm.ll
+++ b/test/CodeGen/AMDGPU/imm.ll
@@ -449,7 +449,7 @@
; SI: v_add_f64 v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}
; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x4c
-; VI: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 0.15915494{{$}}
+; VI: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 0.15915494309189532{{$}}
; VI: buffer_store_dwordx2 [[REG]]
define amdgpu_kernel void @add_inline_imm_inv_2pi_f64(double addrspace(1)* %out, [8 x i32], double %x) {
%y = fadd double %x, 0x3fc45f306dc9c882
diff --git a/test/MC/AMDGPU/literals.s b/test/MC/AMDGPU/literals.s
index c18da5d..486fe82 100644
--- a/test/MC/AMDGPU/literals.s
+++ b/test/MC/AMDGPU/literals.s
@@ -429,7 +429,7 @@
v_trunc_f32_e32 v0, 0x3fc45f306dc9c882
// NOSICI: error: invalid operand for instruction
-// VI: v_fract_f64_e32 v[0:1], 0.15915494 ; encoding: [0xf8,0x64,0x00,0x7e]
+// VI: v_fract_f64_e32 v[0:1], 0.15915494309189532 ; encoding: [0xf8,0x64,0x00,0x7e]
v_fract_f64_e32 v[0:1], 0x3fc45f306dc9c882
// SICI: v_trunc_f32_e32 v0, 0x3e22f983 ; encoding: [0xff,0x42,0x00,0x7e,0x83,0xf9,0x22,0x3e]
@@ -445,7 +445,7 @@
v_trunc_f32_e64 v0, 0x3fc45f306dc9c882
// NOSICI: error: invalid operand for instruction
-// VI: v_fract_f64_e64 v[0:1], 0.15915494 ; encoding: [0x00,0x00,0x72,0xd1,0xf8,0x00,0x00,0x00]
+// VI: v_fract_f64_e64 v[0:1], 0.15915494309189532 ; encoding: [0x00,0x00,0x72,0xd1,0xf8,0x00,0x00,0x00]
v_fract_f64_e64 v[0:1], 0x3fc45f306dc9c882
// NOSICI: error: invalid operand for instruction
@@ -457,7 +457,7 @@
v_fract_f64_e64 v[0:1], 0x3e22f983
// NOSICI: error: invalid operand for instruction
-// VI: s_mov_b64 s[0:1], 0.15915494 ; encoding: [0xf8,0x01,0x80,0xbe]
+// VI: s_mov_b64 s[0:1], 0.15915494309189532 ; encoding: [0xf8,0x01,0x80,0xbe]
s_mov_b64_e32 s[0:1], 0.159154943091895317852646485335
// SICI: v_and_b32_e32 v0, 0x3e22f983, v1 ; encoding: [0xff,0x02,0x00,0x36,0x83,0xf9,0x22,0x3e]
@@ -469,7 +469,7 @@
v_and_b32_e64 v0, 0.159154943091895317852646485335, v1
// SICI: v_fract_f64_e32 v[0:1], 0x3fc45f30 ; encoding: [0xff,0x7c,0x00,0x7e,0x30,0x5f,0xc4,0x3f]
-// VI: v_fract_f64_e32 v[0:1], 0.15915494 ; encoding: [0xf8,0x64,0x00,0x7e]
+// VI: v_fract_f64_e32 v[0:1], 0.15915494309189532 ; encoding: [0xf8,0x64,0x00,0x7e]
v_fract_f64 v[0:1], 0.159154943091895317852646485335
// SICI: v_trunc_f32_e32 v0, 0x3e22f983 ; encoding: [0xff,0x42,0x00,0x7e,0x83,0xf9,0x22,0x3e]
diff --git a/test/MC/Disassembler/AMDGPU/literal_vi.txt b/test/MC/Disassembler/AMDGPU/literal_vi.txt
new file mode 100644
index 0000000..05483cc
--- /dev/null
+++ b/test/MC/Disassembler/AMDGPU/literal_vi.txt
@@ -0,0 +1,7 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding %s | FileCheck -check-prefix=VI %s
+
+# VI: v_fract_f64_e32 v[0:1], 0.15915494309189532 ; encoding: [0xf8,0x64,0x00,0x7e]
+0xf8,0x64,0x00,0x7e
+
+# VI: v_trunc_f32_e32 v0, 0.15915494 ; encoding: [0xf8,0x38,0x00,0x7e]
+0xf8,0x38,0x00,0x7e
