| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s |
| ... |
| --- |
| name: legal_v4s32_v2s32 |
| alignment: 2 |
| legalized: true |
| regBankSelected: true |
| registers: |
| - { id: 0, class: fpr } |
| - { id: 1, class: fpr } |
| - { id: 2, class: fpr } |
| frameInfo: |
| maxCallFrameSize: 0 |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: legal_v4s32_v2s32 |
| ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 |
| ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 |
| ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub |
| ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.dsub |
| ; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0 |
| ; CHECK: $q0 = COPY [[INSvi64lane]] |
| ; CHECK: RET_ReallyLR |
| %0:fpr(<2 x s32>) = COPY $d0 |
| %1:fpr(<2 x s32>) = COPY $d1 |
| %2:fpr(<4 x s32>) = G_CONCAT_VECTORS %0(<2 x s32>), %1(<2 x s32>) |
| $q0 = COPY %2(<4 x s32>) |
| RET_ReallyLR |
| |
| ... |
| --- |
| name: legal_v8s16_v4s16 |
| alignment: 2 |
| legalized: true |
| regBankSelected: true |
| registers: |
| - { id: 0, class: fpr } |
| - { id: 1, class: fpr } |
| - { id: 2, class: fpr } |
| frameInfo: |
| maxCallFrameSize: 0 |
| body: | |
| bb.0: |
| ; CHECK-LABEL: name: legal_v8s16_v4s16 |
| ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 |
| ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 |
| ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub |
| ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.dsub |
| ; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0 |
| ; CHECK: $q0 = COPY [[INSvi64lane]] |
| ; CHECK: RET_ReallyLR |
| %0:fpr(<4 x s16>) = COPY $d0 |
| %1:fpr(<4 x s16>) = COPY $d1 |
| %2:fpr(<8 x s16>) = G_CONCAT_VECTORS %0(<4 x s16>), %1(<4 x s16>) |
| $q0 = COPY %2(<8 x s16>) |
| RET_ReallyLR |
| |
| ... |