| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=regbankselect %s -o - | FileCheck %s |
| |
| name: v2s32_fpr |
| alignment: 2 |
| legalized: true |
| tracksRegLiveness: true |
| registers: |
| - { id: 0, class: _ } |
| - { id: 1, class: _ } |
| - { id: 2, class: _ } |
| body: | |
| bb.1.entry: |
| liveins: $d0 |
| |
| %0:_(<2 x s32>) = COPY $d0 |
| %2:_(s64) = G_CONSTANT i64 1 |
| %1:_(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %2(s64) |
| $s0 = COPY %1(s32) |
| RET_ReallyLR implicit $s0 |
| |
| ... |
| --- |
| name: v4s32_gpr |
| alignment: 2 |
| legalized: true |
| tracksRegLiveness: true |
| registers: |
| - { id: 0, class: _ } |
| - { id: 1, class: _ } |
| - { id: 2, class: _ } |
| body: | |
| bb.1.entry: |
| liveins: $q0 |
| |
| ; CHECK-LABEL: name: v4s32_gpr |
| ; CHECK: liveins: $q0 |
| ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0 |
| ; CHECK: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 0 |
| ; CHECK: [[EVEC:%[0-9]+]]:fpr(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x s32>), [[C]](s64) |
| ; CHECK: $s0 = COPY [[EVEC]](s32) |
| ; CHECK: RET_ReallyLR implicit $s0 |
| %0:_(<4 x s32>) = COPY $q0 |
| %2:_(s64) = G_CONSTANT i64 0 |
| %1:_(s32) = G_EXTRACT_VECTOR_ELT %0(<4 x s32>), %2(s64) |
| $s0 = COPY %1(s32) |
| RET_ReallyLR implicit $s0 |
| |
| ... |
| --- |
| name: v2s64_fpr |
| alignment: 2 |
| legalized: true |
| tracksRegLiveness: true |
| registers: |
| - { id: 0, class: _ } |
| - { id: 1, class: _ } |
| - { id: 2, class: _ } |
| body: | |
| bb.1.entry: |
| liveins: $q0 |
| |
| ; CHECK-LABEL: name: v2s64_fpr |
| ; CHECK: liveins: $q0 |
| ; CHECK: [[COPY:%[0-9]+]]:fpr(<2 x s64>) = COPY $q0 |
| ; CHECK: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 2 |
| ; CHECK: [[EVEC:%[0-9]+]]:fpr(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s64>), [[C]](s64) |
| ; CHECK: $d0 = COPY [[EVEC]](s64) |
| ; CHECK: RET_ReallyLR implicit $d0 |
| %0:_(<2 x s64>) = COPY $q0 |
| %2:_(s64) = G_CONSTANT i64 2 |
| %1:_(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %2(s64) |
| $d0 = COPY %1(s64) |
| RET_ReallyLR implicit $d0 |
| |
| ... |
| --- |
| name: v4s16_fpr |
| alignment: 2 |
| legalized: true |
| tracksRegLiveness: true |
| registers: |
| - { id: 0, class: _ } |
| - { id: 1, class: _ } |
| - { id: 2, class: _ } |
| body: | |
| bb.1.entry: |
| liveins: $d0 |
| |
| ; CHECK-LABEL: name: v4s16_fpr |
| ; CHECK: liveins: $d0 |
| ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s16>) = COPY $d0 |
| ; CHECK: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 1 |
| ; CHECK: [[EVEC:%[0-9]+]]:fpr(s16) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x s16>), [[C]](s64) |
| ; CHECK: $h0 = COPY [[EVEC]](s16) |
| ; CHECK: RET_ReallyLR implicit $h0 |
| %0:_(<4 x s16>) = COPY $d0 |
| %2:_(s64) = G_CONSTANT i64 1 |
| %1:_(s16) = G_EXTRACT_VECTOR_ELT %0(<4 x s16>), %2(s64) |
| $h0 = COPY %1(s16) |
| RET_ReallyLR implicit $h0 |
| |
| ... |