test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s

---
name: test_sitofp_s32_to_s32
body: |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_sitofp_s32_to_s32
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY]](s32)
    ; CHECK: $vgpr0 = COPY [[SITOFP]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = G_SITOFP %0
    $vgpr0 = COPY %1
...

---
name: test_sitofp_s32_to_s64
body: |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: test_sitofp_s32_to_s64
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[COPY]](s32)
    ; CHECK: $vgpr0_vgpr1 = COPY [[SITOFP]](s64)
    %0:_(s32) = COPY $vgpr0
    %1:_(s64) = G_SITOFP %0
    $vgpr0_vgpr1 = COPY %1
...

---
name: test_sitofp_v2s32_to_v2s32
body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: test_sitofp_v2s32_to_v2s32
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
    ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[UV]](s32)
    ; CHECK: [[SITOFP1:%[0-9]+]]:_(s32) = G_SITOFP [[UV1]](s32)
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SITOFP]](s32), [[SITOFP1]](s32)
    ; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
    %1:_(<2 x s32>) = G_SITOFP %0
    $vgpr0_vgpr1 = COPY %1
...

---
name: test_sitofp_v2s32_to_v2s64
body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: test_sitofp_v2s32_to_v2s64
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
    ; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[UV]](s32)
    ; CHECK: [[SITOFP1:%[0-9]+]]:_(s64) = G_SITOFP [[UV1]](s32)
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SITOFP]](s64), [[SITOFP1]](s64)
    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
    %1:_(<2 x s64>) = G_SITOFP %0
    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
...

---
name: test_sitofp_s64_to_s32
body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: test_sitofp_s64_to_s32
    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[TRUNC]](s32)
    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
    ; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR]](s64)
    ; CHECK: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
    ; CHECK: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV]], [[UV2]], [[C1]]
    ; CHECK: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV3]], [[UADDE1]]
    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDE]](s32), [[UADDE2]](s32)
    ; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[MV]], [[ASHR]]
    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
    ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[XOR]](s64)
    ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 190
    ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[CTLZ_ZERO_UNDEF]]
    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[XOR]](s64), [[C3]]
    ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB]], [[C2]]
    ; CHECK: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807
    ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[XOR]], [[CTLZ_ZERO_UNDEF]](s32)
    ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C5]]
    ; CHECK: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1099511627775
    ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C6]]
    ; CHECK: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C7]](s64)
    ; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[TRUNC1]](s32)
    ; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SELECT]], [[C8]](s32)
    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[TRUNC2]]
    ; CHECK: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 549755813888
    ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[AND1]](s64), [[C9]]
    ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND1]](s64), [[C9]]
    ; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
    ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C10]]
    ; CHECK: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[AND2]], [[C2]]
    ; CHECK: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[C10]], [[SELECT1]]
    ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[OR]], [[SELECT2]]
    ; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[XOR]](s64)
    ; CHECK: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[UITOFP]]
    ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ASHR]](s64), [[C3]]
    ; CHECK: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[FNEG]], [[UITOFP]]
    ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY]](s64)
    ; CHECK: $vgpr0 = COPY [[SITOFP]](s32)
    %0:_(s64) = COPY $vgpr0_vgpr1
    %1:_(s32) = G_SITOFP %0
    $vgpr0 = COPY %1
...

---
name: test_sitofp_s64_to_s64
body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: test_sitofp_s64_to_s64
    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
    ; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[UV1]](s32)
    ; CHECK: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[UV]](s32)
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
    ; CHECK: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), [[SITOFP]](s64), [[C]](s32)
    ; CHECK: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[INT]], [[UITOFP]]
    ; CHECK: $vgpr0_vgpr1 = COPY [[FADD]](s64)
    %0:_(s64) = COPY $vgpr0_vgpr1
    %1:_(s64) = G_SITOFP %0
    $vgpr0_vgpr1 = COPY %1
...