| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s |
| |
| --- | |
| |
| define signext i8 @float_to_int8(float %val) { |
| entry: |
| %conv = fptosi float %val to i8 |
| ret i8 %conv |
| } |
| |
| define signext i16 @float_to_int16(float %val) { |
| entry: |
| %conv = fptosi float %val to i16 |
| ret i16 %conv |
| } |
| |
| define i32 @float_to_int32(float %val) { |
| entry: |
| %conv = fptosi float %val to i32 |
| ret i32 %conv |
| } |
| |
| define i64 @float_to_int64(float %val) { |
| entry: |
| %conv = fptosi float %val to i64 |
| ret i64 %conv |
| } |
| |
| define signext i8 @double_to_int8(double %val) { |
| entry: |
| %conv = fptosi double %val to i8 |
| ret i8 %conv |
| } |
| |
| define signext i16 @double_to_int16(double %val) { |
| entry: |
| %conv = fptosi double %val to i16 |
| ret i16 %conv |
| } |
| |
| define i32 @double_to_int32(double %val) { |
| entry: |
| %conv = fptosi double %val to i32 |
| ret i32 %conv |
| } |
| |
| define i64 @double_to_int64(double %val) { |
| entry: |
| %conv = fptosi double %val to i64 |
| ret i64 %conv |
| } |
| |
| ... |
| --- |
| name: float_to_int8 |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| registers: |
| - { id: 0, class: vecr } |
| - { id: 1, class: vecr } |
| - { id: 2, class: gpr } |
| - { id: 3, class: gpr } |
| body: | |
| bb.1.entry: |
| liveins: $xmm0 |
| |
| ; CHECK-LABEL: name: float_to_int8 |
| ; CHECK: liveins: $xmm0 |
| ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 |
| ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] |
| ; CHECK: [[CVTTSS2SIrr:%[0-9]+]]:gr32 = CVTTSS2SIrr [[COPY1]] |
| ; CHECK: [[COPY2:%[0-9]+]]:gr8 = COPY [[CVTTSS2SIrr]].sub_8bit |
| ; CHECK: $al = COPY [[COPY2]] |
| ; CHECK: RET 0, implicit $al |
| %1:vecr(s128) = COPY $xmm0 |
| %0:vecr(s32) = G_TRUNC %1(s128) |
| %3:gpr(s32) = G_FPTOSI %0(s32) |
| %2:gpr(s8) = G_TRUNC %3(s32) |
| $al = COPY %2(s8) |
| RET 0, implicit $al |
| |
| ... |
| --- |
| name: float_to_int16 |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| registers: |
| - { id: 0, class: vecr } |
| - { id: 1, class: vecr } |
| - { id: 2, class: gpr } |
| - { id: 3, class: gpr } |
| body: | |
| bb.1.entry: |
| liveins: $xmm0 |
| |
| ; CHECK-LABEL: name: float_to_int16 |
| ; CHECK: liveins: $xmm0 |
| ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 |
| ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] |
| ; CHECK: [[CVTTSS2SIrr:%[0-9]+]]:gr32 = CVTTSS2SIrr [[COPY1]] |
| ; CHECK: [[COPY2:%[0-9]+]]:gr16 = COPY [[CVTTSS2SIrr]].sub_16bit |
| ; CHECK: $ax = COPY [[COPY2]] |
| ; CHECK: RET 0, implicit $ax |
| %1:vecr(s128) = COPY $xmm0 |
| %0:vecr(s32) = G_TRUNC %1(s128) |
| %3:gpr(s32) = G_FPTOSI %0(s32) |
| %2:gpr(s16) = G_TRUNC %3(s32) |
| $ax = COPY %2(s16) |
| RET 0, implicit $ax |
| |
| ... |
| --- |
| name: float_to_int32 |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| registers: |
| - { id: 0, class: vecr } |
| - { id: 1, class: vecr } |
| - { id: 2, class: gpr } |
| body: | |
| bb.1.entry: |
| liveins: $xmm0 |
| |
| ; CHECK-LABEL: name: float_to_int32 |
| ; CHECK: liveins: $xmm0 |
| ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 |
| ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] |
| ; CHECK: [[CVTTSS2SIrr:%[0-9]+]]:gr32 = CVTTSS2SIrr [[COPY1]] |
| ; CHECK: $eax = COPY [[CVTTSS2SIrr]] |
| ; CHECK: RET 0, implicit $eax |
| %1:vecr(s128) = COPY $xmm0 |
| %0:vecr(s32) = G_TRUNC %1(s128) |
| %2:gpr(s32) = G_FPTOSI %0(s32) |
| $eax = COPY %2(s32) |
| RET 0, implicit $eax |
| |
| ... |
| --- |
| name: float_to_int64 |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| registers: |
| - { id: 0, class: vecr } |
| - { id: 1, class: vecr } |
| - { id: 2, class: gpr } |
| body: | |
| bb.1.entry: |
| liveins: $xmm0 |
| |
| ; CHECK-LABEL: name: float_to_int64 |
| ; CHECK: liveins: $xmm0 |
| ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 |
| ; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]] |
| ; CHECK: [[CVTTSS2SI64rr:%[0-9]+]]:gr64 = CVTTSS2SI64rr [[COPY1]] |
| ; CHECK: $rax = COPY [[CVTTSS2SI64rr]] |
| ; CHECK: RET 0, implicit $rax |
| %1:vecr(s128) = COPY $xmm0 |
| %0:vecr(s32) = G_TRUNC %1(s128) |
| %2:gpr(s64) = G_FPTOSI %0(s32) |
| $rax = COPY %2(s64) |
| RET 0, implicit $rax |
| |
| ... |
| --- |
| name: double_to_int8 |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| registers: |
| - { id: 0, class: vecr } |
| - { id: 1, class: vecr } |
| - { id: 2, class: gpr } |
| - { id: 3, class: gpr } |
| body: | |
| bb.1.entry: |
| liveins: $xmm0 |
| |
| ; CHECK-LABEL: name: double_to_int8 |
| ; CHECK: liveins: $xmm0 |
| ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 |
| ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] |
| ; CHECK: [[CVTTSD2SIrr:%[0-9]+]]:gr32 = CVTTSD2SIrr [[COPY1]] |
| ; CHECK: [[COPY2:%[0-9]+]]:gr8 = COPY [[CVTTSD2SIrr]].sub_8bit |
| ; CHECK: $al = COPY [[COPY2]] |
| ; CHECK: RET 0, implicit $al |
| %1:vecr(s128) = COPY $xmm0 |
| %0:vecr(s64) = G_TRUNC %1(s128) |
| %3:gpr(s32) = G_FPTOSI %0(s64) |
| %2:gpr(s8) = G_TRUNC %3(s32) |
| $al = COPY %2(s8) |
| RET 0, implicit $al |
| |
| ... |
| --- |
| name: double_to_int16 |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| registers: |
| - { id: 0, class: vecr } |
| - { id: 1, class: vecr } |
| - { id: 2, class: gpr } |
| - { id: 3, class: gpr } |
| body: | |
| bb.1.entry: |
| liveins: $xmm0 |
| |
| ; CHECK-LABEL: name: double_to_int16 |
| ; CHECK: liveins: $xmm0 |
| ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 |
| ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] |
| ; CHECK: [[CVTTSD2SIrr:%[0-9]+]]:gr32 = CVTTSD2SIrr [[COPY1]] |
| ; CHECK: [[COPY2:%[0-9]+]]:gr16 = COPY [[CVTTSD2SIrr]].sub_16bit |
| ; CHECK: $ax = COPY [[COPY2]] |
| ; CHECK: RET 0, implicit $ax |
| %1:vecr(s128) = COPY $xmm0 |
| %0:vecr(s64) = G_TRUNC %1(s128) |
| %3:gpr(s32) = G_FPTOSI %0(s64) |
| %2:gpr(s16) = G_TRUNC %3(s32) |
| $ax = COPY %2(s16) |
| RET 0, implicit $ax |
| |
| ... |
| --- |
| name: double_to_int32 |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| registers: |
| - { id: 0, class: vecr } |
| - { id: 1, class: vecr } |
| - { id: 2, class: gpr } |
| body: | |
| bb.1.entry: |
| liveins: $xmm0 |
| |
| ; CHECK-LABEL: name: double_to_int32 |
| ; CHECK: liveins: $xmm0 |
| ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 |
| ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] |
| ; CHECK: [[CVTTSD2SIrr:%[0-9]+]]:gr32 = CVTTSD2SIrr [[COPY1]] |
| ; CHECK: $eax = COPY [[CVTTSD2SIrr]] |
| ; CHECK: RET 0, implicit $eax |
| %1:vecr(s128) = COPY $xmm0 |
| %0:vecr(s64) = G_TRUNC %1(s128) |
| %2:gpr(s32) = G_FPTOSI %0(s64) |
| $eax = COPY %2(s32) |
| RET 0, implicit $eax |
| |
| ... |
| --- |
| name: double_to_int64 |
| alignment: 4 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| registers: |
| - { id: 0, class: vecr } |
| - { id: 1, class: vecr } |
| - { id: 2, class: gpr } |
| body: | |
| bb.1.entry: |
| liveins: $xmm0 |
| |
| ; CHECK-LABEL: name: double_to_int64 |
| ; CHECK: liveins: $xmm0 |
| ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0 |
| ; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]] |
| ; CHECK: [[CVTTSD2SI64rr:%[0-9]+]]:gr64 = CVTTSD2SI64rr [[COPY1]] |
| ; CHECK: $rax = COPY [[CVTTSD2SI64rr]] |
| ; CHECK: RET 0, implicit $rax |
| %1:vecr(s128) = COPY $xmm0 |
| %0:vecr(s64) = G_TRUNC %1(s128) |
| %2:gpr(s64) = G_FPTOSI %0(s64) |
| $rax = COPY %2(s64) |
| RET 0, implicit $rax |
| |
| ... |