| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse3 | FileCheck %s --check-prefix=SSE3 |
| ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE41 |
| ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX-32 |
| ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX-32 |
| ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX-64 |
| |
| define <3 x i16> @zext_i8(<3 x i8>) { |
| ; SSE3-LABEL: zext_i8: |
| ; SSE3: # %bb.0: |
| ; SSE3-NEXT: movzbl {{[0-9]+}}(%esp), %eax |
| ; SSE3-NEXT: movzbl {{[0-9]+}}(%esp), %ecx |
| ; SSE3-NEXT: movzbl {{[0-9]+}}(%esp), %edx |
| ; SSE3-NEXT: movd %edx, %xmm0 |
| ; SSE3-NEXT: pinsrw $1, %ecx, %xmm0 |
| ; SSE3-NEXT: pinsrw $2, %eax, %xmm0 |
| ; SSE3-NEXT: retl |
| ; |
| ; SSE41-LABEL: zext_i8: |
| ; SSE41: # %bb.0: |
| ; SSE41-NEXT: pxor %xmm0, %xmm0 |
| ; SSE41-NEXT: pinsrb $0, {{[0-9]+}}(%esp), %xmm0 |
| ; SSE41-NEXT: pinsrb $2, {{[0-9]+}}(%esp), %xmm0 |
| ; SSE41-NEXT: pinsrb $4, {{[0-9]+}}(%esp), %xmm0 |
| ; SSE41-NEXT: retl |
| ; |
| ; AVX-32-LABEL: zext_i8: |
| ; AVX-32: # %bb.0: |
| ; AVX-32-NEXT: vpxor %xmm0, %xmm0, %xmm0 |
| ; AVX-32-NEXT: vpinsrb $0, {{[0-9]+}}(%esp), %xmm0, %xmm0 |
| ; AVX-32-NEXT: vpinsrb $2, {{[0-9]+}}(%esp), %xmm0, %xmm0 |
| ; AVX-32-NEXT: vpinsrb $4, {{[0-9]+}}(%esp), %xmm0, %xmm0 |
| ; AVX-32-NEXT: retl |
| ; |
| ; AVX-64-LABEL: zext_i8: |
| ; AVX-64: # %bb.0: |
| ; AVX-64-NEXT: vpxor %xmm0, %xmm0, %xmm0 |
| ; AVX-64-NEXT: vpinsrb $0, %edi, %xmm0, %xmm0 |
| ; AVX-64-NEXT: vpinsrb $2, %esi, %xmm0, %xmm0 |
| ; AVX-64-NEXT: vpinsrb $4, %edx, %xmm0, %xmm0 |
| ; AVX-64-NEXT: retq |
| %2 = zext <3 x i8> %0 to <3 x i16> |
| ret <3 x i16> %2 |
| } |
| |
| define <3 x i16> @sext_i8(<3 x i8>) { |
| ; SSE3-LABEL: sext_i8: |
| ; SSE3: # %bb.0: |
| ; SSE3-NEXT: movsbl {{[0-9]+}}(%esp), %eax |
| ; SSE3-NEXT: movd %eax, %xmm0 |
| ; SSE3-NEXT: movsbl {{[0-9]+}}(%esp), %eax |
| ; SSE3-NEXT: pinsrw $1, %eax, %xmm0 |
| ; SSE3-NEXT: movsbl {{[0-9]+}}(%esp), %eax |
| ; SSE3-NEXT: pinsrw $2, %eax, %xmm0 |
| ; SSE3-NEXT: retl |
| ; |
| ; SSE41-LABEL: sext_i8: |
| ; SSE41: # %bb.0: |
| ; SSE41-NEXT: movsbl {{[0-9]+}}(%esp), %eax |
| ; SSE41-NEXT: movd %eax, %xmm0 |
| ; SSE41-NEXT: movsbl {{[0-9]+}}(%esp), %eax |
| ; SSE41-NEXT: pinsrw $1, %eax, %xmm0 |
| ; SSE41-NEXT: movsbl {{[0-9]+}}(%esp), %eax |
| ; SSE41-NEXT: pinsrw $2, %eax, %xmm0 |
| ; SSE41-NEXT: retl |
| ; |
| ; AVX-32-LABEL: sext_i8: |
| ; AVX-32: # %bb.0: |
| ; AVX-32-NEXT: movsbl {{[0-9]+}}(%esp), %eax |
| ; AVX-32-NEXT: vmovd %eax, %xmm0 |
| ; AVX-32-NEXT: movsbl {{[0-9]+}}(%esp), %eax |
| ; AVX-32-NEXT: vpinsrw $1, %eax, %xmm0, %xmm0 |
| ; AVX-32-NEXT: movsbl {{[0-9]+}}(%esp), %eax |
| ; AVX-32-NEXT: vpinsrw $2, %eax, %xmm0, %xmm0 |
| ; AVX-32-NEXT: retl |
| ; |
| ; AVX-64-LABEL: sext_i8: |
| ; AVX-64: # %bb.0: |
| ; AVX-64-NEXT: movsbl %sil, %eax |
| ; AVX-64-NEXT: movsbl %dil, %ecx |
| ; AVX-64-NEXT: vmovd %ecx, %xmm0 |
| ; AVX-64-NEXT: vpinsrw $1, %eax, %xmm0, %xmm0 |
| ; AVX-64-NEXT: movsbl %dl, %eax |
| ; AVX-64-NEXT: vpinsrw $2, %eax, %xmm0, %xmm0 |
| ; AVX-64-NEXT: retq |
| %2 = sext <3 x i8> %0 to <3 x i16> |
| ret <3 x i16> %2 |
| } |