| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s |
| # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s |
| # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s |
| |
| --- |
| name: add_s32 |
| legalized: true |
| regBankSelected: true |
| |
| body: | |
| bb.0: |
| liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4 |
| |
| |
| ; GFX6-LABEL: name: add_s32 |
| ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 |
| ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX6: [[S_ADD_U32_:%[0-9]+]]:sreg_32_xm0 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc |
| ; GFX6: %7:vgpr_32, dead %12:sreg_64_xexec = V_ADD_I32_e64 [[COPY2]], [[S_ADD_U32_]], 0, implicit $exec |
| ; GFX6: %8:vgpr_32, dead %11:sreg_64_xexec = V_ADD_I32_e64 [[S_ADD_U32_]], %7, 0, implicit $exec |
| ; GFX6: %9:vgpr_32, dead %10:sreg_64_xexec = V_ADD_I32_e64 %8, [[COPY2]], 0, implicit $exec |
| ; GFX6: S_ENDPGM 0, implicit %9 |
| ; GFX9-LABEL: name: add_s32 |
| ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 |
| ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 |
| ; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0 |
| ; GFX9: [[S_ADD_U32_:%[0-9]+]]:sreg_32_xm0 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc |
| ; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY2]], [[S_ADD_U32_]], 0, implicit $exec |
| ; GFX9: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_ADD_U32_]], [[V_ADD_U32_e64_]], 0, implicit $exec |
| ; GFX9: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_1]], [[COPY2]], 0, implicit $exec |
| ; GFX9: S_ENDPGM 0, implicit [[V_ADD_U32_e64_2]] |
| %0:sgpr(s32) = COPY $sgpr0 |
| %1:sgpr(s32) = COPY $sgpr1 |
| %2:vgpr(s32) = COPY $vgpr0 |
| %3:vgpr(p1) = COPY $vgpr3_vgpr4 |
| %4:sgpr(s32) = G_CONSTANT i32 1 |
| %5:sgpr(s32) = G_CONSTANT i32 4096 |
| |
| ; add ss |
| %6:sgpr(s32) = G_ADD %0, %1 |
| |
| ; add vs |
| %7:vgpr(s32) = G_ADD %2, %6 |
| |
| ; add sv |
| %8:vgpr(s32) = G_ADD %6, %7 |
| |
| ; add vv |
| %9:vgpr(s32) = G_ADD %8, %2 |
| |
| S_ENDPGM 0, implicit %9 |
| |
| ... |