| //===-- Sparc.td - Describe the Sparc Target Machine -------*- tablegen -*-===// |
| // |
| // The LLVM Compiler Infrastructure |
| // |
| // This file is distributed under the University of Illinois Open Source |
| // License. See LICENSE.TXT for details. |
| // |
| //===----------------------------------------------------------------------===// |
| // |
| // |
| //===----------------------------------------------------------------------===// |
| |
| //===----------------------------------------------------------------------===// |
| // Target-independent interfaces which we are implementing |
| //===----------------------------------------------------------------------===// |
| |
| include "llvm/Target/Target.td" |
| |
| //===----------------------------------------------------------------------===// |
| // SPARC Subtarget features. |
| // |
| |
| def FeatureV9 |
| : SubtargetFeature<"v9", "IsV9", "true", |
| "Enable SPARC-V9 instructions">; |
| def FeatureV8Deprecated |
| : SubtargetFeature<"deprecated-v8", "V8DeprecatedInsts", "true", |
| "Enable deprecated V8 instructions in V9 mode">; |
| def FeatureVIS |
| : SubtargetFeature<"vis", "IsVIS", "true", |
| "Enable UltraSPARC Visual Instruction Set extensions">; |
| def FeatureVIS2 |
| : SubtargetFeature<"vis2", "IsVIS2", "true", |
| "Enable Visual Instruction Set extensions II">; |
| def FeatureVIS3 |
| : SubtargetFeature<"vis3", "IsVIS3", "true", |
| "Enable Visual Instruction Set extensions III">; |
| |
| def FeatureHardQuad |
| : SubtargetFeature<"hard-quad-float", "HasHardQuad", "true", |
| "Enable quad-word floating point instructions">; |
| |
| def UsePopc : SubtargetFeature<"popc", "UsePopc", "true", |
| "Use the popc (population count) instruction">; |
| |
| //===----------------------------------------------------------------------===// |
| // Register File, Calling Conv, Instruction Descriptions |
| //===----------------------------------------------------------------------===// |
| |
| include "SparcRegisterInfo.td" |
| include "SparcCallingConv.td" |
| include "SparcInstrInfo.td" |
| |
| def SparcInstrInfo : InstrInfo; |
| |
| def SparcAsmParser : AsmParser { |
| bit ShouldEmitMatchRegisterName = 0; |
| } |
| |
| //===----------------------------------------------------------------------===// |
| // SPARC processors supported. |
| //===----------------------------------------------------------------------===// |
| |
| class Proc<string Name, list<SubtargetFeature> Features> |
| : Processor<Name, NoItineraries, Features>; |
| |
| def : Proc<"generic", []>; |
| def : Proc<"v7", []>; |
| def : Proc<"v8", []>; |
| def : Proc<"supersparc", []>; |
| def : Proc<"sparclite", []>; |
| def : Proc<"f934", []>; |
| def : Proc<"hypersparc", []>; |
| def : Proc<"sparclite86x", []>; |
| def : Proc<"sparclet", []>; |
| def : Proc<"tsc701", []>; |
| def : Proc<"v9", [FeatureV9]>; |
| def : Proc<"ultrasparc", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>; |
| def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated, FeatureVIS, |
| FeatureVIS2]>; |
| def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS, |
| FeatureVIS2]>; |
| def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc, |
| FeatureVIS, FeatureVIS2]>; |
| def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc, |
| FeatureVIS, FeatureVIS2]>; |
| def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc, |
| FeatureVIS, FeatureVIS2, FeatureVIS3]>; |
| |
| |
| //===----------------------------------------------------------------------===// |
| // Declare the target which we are implementing |
| //===----------------------------------------------------------------------===// |
| |
| def SparcAsmWriter : AsmWriter { |
| string AsmWriterClassName = "InstPrinter"; |
| int PassSubtarget = 1; |
| int Variant = 0; |
| } |
| |
| def Sparc : Target { |
| // Pull in Instruction Info: |
| let InstructionSet = SparcInstrInfo; |
| let AssemblyParsers = [SparcAsmParser]; |
| let AssemblyWriters = [SparcAsmWriter]; |
| } |
