[ARM GlobalISel] Support branches for Thumb2
Just like arm mode, but with different opcodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354113 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMInstructionSelector.cpp b/lib/Target/ARM/ARMInstructionSelector.cpp
index 262300e..3030e21 100644
--- a/lib/Target/ARM/ARMInstructionSelector.cpp
+++ b/lib/Target/ARM/ARMInstructionSelector.cpp
@@ -106,6 +106,9 @@
unsigned CMPri;
unsigned MOVCCr;
+ unsigned TSTri;
+ unsigned Bcc;
+
OpcodeCache(const ARMSubtarget &STI);
} const Opcodes;
@@ -300,6 +303,9 @@
STORE_OPCODE(CMPri, CMPri);
STORE_OPCODE(MOVCCr, MOVCCr);
+
+ STORE_OPCODE(TSTri, TSTri);
+ STORE_OPCODE(Bcc, Bcc);
#undef MAP_OPCODE
}
@@ -1008,17 +1014,19 @@
}
// Set the flags.
- auto Test = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(ARM::TSTri))
- .addReg(I.getOperand(0).getReg())
- .addImm(1)
- .add(predOps(ARMCC::AL));
+ auto Test =
+ BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcodes.TSTri))
+ .addReg(I.getOperand(0).getReg())
+ .addImm(1)
+ .add(predOps(ARMCC::AL));
if (!constrainSelectedInstRegOperands(*Test, TII, TRI, RBI))
return false;
// Branch conditionally.
- auto Branch = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(ARM::Bcc))
- .add(I.getOperand(1))
- .add(predOps(ARMCC::NE, ARM::CPSR));
+ auto Branch =
+ BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcodes.Bcc))
+ .add(I.getOperand(1))
+ .add(predOps(ARMCC::NE, ARM::CPSR));
if (!constrainSelectedInstRegOperands(*Branch, TII, TRI, RBI))
return false;
I.eraseFromParent();
diff --git a/lib/Target/ARM/ARMLegalizerInfo.cpp b/lib/Target/ARM/ARMLegalizerInfo.cpp
index 2b217ce..0794e17 100644
--- a/lib/Target/ARM/ARMLegalizerInfo.cpp
+++ b/lib/Target/ARM/ARMLegalizerInfo.cpp
@@ -140,6 +140,8 @@
getActionDefinitionsBuilder(G_GEP).legalFor({{p0, s32}});
+ getActionDefinitionsBuilder(G_BRCOND).legalFor({s1});
+
if (ST.isThumb()) {
// FIXME: merge with the code for non-Thumb.
computeTables();
@@ -170,8 +172,6 @@
.clampScalar(0, s32, s32);
}
- getActionDefinitionsBuilder(G_BRCOND).legalFor({s1});
-
// We're keeping these builders around because we'll want to add support for
// floating point to them.
auto &PhiBuilder =
diff --git a/test/CodeGen/ARM/GlobalISel/arm-legalize-control-flow.mir b/test/CodeGen/ARM/GlobalISel/arm-legalize-control-flow.mir
new file mode 100644
index 0000000..f3013fc
--- /dev/null
+++ b/test/CodeGen/ARM/GlobalISel/arm-legalize-control-flow.mir
@@ -0,0 +1,39 @@
+# RUN: llc -mtriple arm-- -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple thumb-- -mattr=+v6t2 -run-pass=legalizer %s -o - | FileCheck %s
+--- |
+ define void @test_brcond() { ret void }
+...
+---
+name: test_brcond
+# CHECK-LABEL: name: test_brcond
+legalized: false
+# CHECK: legalized: true
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.0:
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $r0, $r1
+
+ %0(s32) = COPY $r0
+ %1(s32) = COPY $r1
+ %2(s1) = G_ICMP intpred(sgt), %0(s32), %1
+ G_BRCOND %2(s1), %bb.1
+ ; G_BRCOND with s1 is legal, so we should find it unchanged in the output
+ ; CHECK: G_BRCOND {{%[0-9]+}}(s1), %bb.1
+ G_BR %bb.2
+
+ bb.1:
+ $r0 = COPY %1(s32)
+ BX_RET 14, $noreg, implicit $r0
+
+ bb.2:
+ $r0 = COPY %0(s32)
+ BX_RET 14, $noreg, implicit $r0
+
+...
diff --git a/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir b/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
index e74366d..3a0d0b6 100644
--- a/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
@@ -5,7 +5,6 @@
define void @test_constants_s64() { ret void }
- define void @test_brcond() { ret void }
define void @test_phi_s32() { ret void }
define void @test_phi_p0() { ret void }
@@ -105,40 +104,6 @@
BX_RET 14, $noreg
...
---
-name: test_brcond
-# CHECK-LABEL: name: test_brcond
-legalized: false
-# CHECK: legalized: true
-regBankSelected: false
-selected: false
-tracksRegLiveness: true
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
-body: |
- bb.0:
- successors: %bb.1(0x40000000), %bb.2(0x40000000)
- liveins: $r0, $r1
-
- %0(s32) = COPY $r0
- %1(s32) = COPY $r1
- %2(s1) = G_ICMP intpred(sgt), %0(s32), %1
- G_BRCOND %2(s1), %bb.1
- ; G_BRCOND with s1 is legal, so we should find it unchanged in the output
- ; CHECK: G_BRCOND {{%[0-9]+}}(s1), %bb.1
- G_BR %bb.2
-
- bb.1:
- $r0 = COPY %1(s32)
- BX_RET 14, $noreg, implicit $r0
-
- bb.2:
- $r0 = COPY %0(s32)
- BX_RET 14, $noreg, implicit $r0
-
-...
----
name: test_phi_s32
# CHECK-LABEL: name: test_phi_s32
legalized: false
diff --git a/test/CodeGen/ARM/GlobalISel/thumb-select-br.mir b/test/CodeGen/ARM/GlobalISel/thumb-select-br.mir
new file mode 100644
index 0000000..e7cec02
--- /dev/null
+++ b/test/CodeGen/ARM/GlobalISel/thumb-select-br.mir
@@ -0,0 +1,44 @@
+# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+--- |
+ define void @test_br() { ret void }
+...
+---
+name: test_br
+# CHECK-LABEL: name: test_br
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+body: |
+ bb.0:
+ ; CHECK: bb.0
+ successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ liveins: $r0
+
+ %0(s32) = COPY $r0
+ ; CHECK: [[COND32:%[0-9]+]]:gpr = COPY $r0
+ %1(s1) = G_TRUNC %0(s32)
+ ; CHECK: [[COND:%[0-9]+]]:gprnopc = COPY [[COND32]]
+
+ G_BRCOND %1(s1), %bb.1
+ ; CHECK: t2TSTri [[COND]], 1, 14, $noreg, implicit-def $cpsr
+ ; CHECK: t2Bcc %bb.1, 1, $cpsr
+ G_BR %bb.2
+ ; CHECK: t2B %bb.2, 14, $noreg
+
+ bb.1:
+ ; CHECK: bb.1
+ successors: %bb.2(0x80000000)
+
+ G_BR %bb.2
+ ; CHECK: t2B %bb.2, 14, $noreg
+
+ bb.2:
+ ; CHECK: bb.2
+
+ tBX_RET 14, $noreg
+ ; CHECK: tBX_RET 14, $noreg
+...
