| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -O0 -march=amdgcn -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s |
| |
| --- |
| name: test_fcmp_s32 |
| body: | |
| bb.0.entry: |
| liveins: $vgpr0 |
| ; CHECK-LABEL: name: test_fcmp_s32 |
| ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[C]](s32), [[COPY]] |
| ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C]], [[COPY]] |
| ; CHECK: $vgpr0 = COPY [[SELECT]](s32) |
| %0:_(s32) = G_CONSTANT i32 0 |
| %1:_(s32) = COPY $vgpr0 |
| %2:_(s1) = G_FCMP floatpred(oeq), %0, %1 |
| %3:_(s32) = G_SELECT %2, %0, %1 |
| $vgpr0 = COPY %3 |
| ... |
| |
| --- |
| name: test_fcmp_s64 |
| body: | |
| bb.0.entry: |
| liveins: $vgpr0_vgpr1 |
| ; CHECK-LABEL: name: test_fcmp_s64 |
| ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 |
| ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 |
| ; CHECK: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[C]](s64), [[COPY]] |
| ; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[C]], [[COPY]] |
| ; CHECK: $vgpr0_vgpr1 = COPY [[SELECT]](s64) |
| %0:_(s64) = G_CONSTANT i64 0 |
| %1:_(s64) = COPY $vgpr0_vgpr1 |
| %2:_(s1) = G_FCMP floatpred(oeq), %0, %1 |
| %3:_(s64) = G_SELECT %2, %0, %1 |
| $vgpr0_vgpr1 = COPY %3 |
| ... |
| |
| --- |
| name: test_fcmp_s16 |
| body: | |
| bb.0.entry: |
| liveins: $vgpr0 |
| ; CHECK-LABEL: name: test_fcmp_s16 |
| ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32) |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) |
| ; CHECK: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16) |
| ; CHECK: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC1]](s16) |
| ; CHECK: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[FPEXT]](s32), [[FPEXT1]] |
| ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32) |
| ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) |
| ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[COPY1]], [[COPY2]] |
| ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) |
| ; CHECK: $vgpr0 = COPY [[COPY3]](s32) |
| %0:_(s16) = G_CONSTANT i16 0 |
| %1:_(s32) = COPY $vgpr0 |
| %2:_(s16) = G_TRUNC %1 |
| %3:_(s1) = G_FCMP floatpred(oeq), %0, %2 |
| %4:_(s16) = G_SELECT %3, %0, %2 |
| %5:_(s32) = G_ANYEXT %4 |
| $vgpr0 = COPY %5 |
| ... |
| |
| --- |
| name: test_fcmp_v2s32 |
| body: | |
| bb.0.entry: |
| liveins: $vgpr0_vgpr1 |
| ; CHECK-LABEL: name: test_fcmp_v2s32 |
| ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 |
| ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) |
| ; CHECK: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[C]](s32), [[UV]] |
| ; CHECK: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[C]](s32), [[UV1]] |
| ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s1>) = G_BUILD_VECTOR [[FCMP]](s1), [[FCMP1]](s1) |
| ; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<2 x s1>) |
| %0:_(s32) = G_CONSTANT i32 0 |
| %1:_(<2 x s32>) = G_BUILD_VECTOR %0, %0 |
| %2:_(<2 x s32>) = COPY $vgpr0_vgpr1 |
| %3:_(<2 x s1>) = G_FCMP floatpred(oeq), %1, %2 |
| S_NOP 0, implicit %3 |
| ... |
| |
| --- |
| name: test_fcmp_v2s32_flags |
| body: | |
| bb.0.entry: |
| liveins: $vgpr0_vgpr1 |
| ; CHECK-LABEL: name: test_fcmp_v2s32_flags |
| ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 |
| ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) |
| ; CHECK: %8:_(s1) = nnan G_FCMP floatpred(oeq), [[C]](s32), [[UV]] |
| ; CHECK: %9:_(s1) = nnan G_FCMP floatpred(oeq), [[C]](s32), [[UV1]] |
| ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s1>) = G_BUILD_VECTOR %8(s1), %9(s1) |
| ; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<2 x s1>) |
| %0:_(s32) = G_CONSTANT i32 0 |
| %1:_(<2 x s32>) = G_BUILD_VECTOR %0, %0 |
| %2:_(<2 x s32>) = COPY $vgpr0_vgpr1 |
| %3:_(<2 x s1>) = nnan G_FCMP floatpred(oeq), %1, %2 |
| S_NOP 0, implicit %3 |
| ... |
| |
| --- |
| name: test_fcmp_v3s32 |
| body: | |
| bb.0.entry: |
| liveins: $vgpr0_vgpr1_vgpr2 |
| |
| ; CHECK-LABEL: name: test_fcmp_v3s32 |
| ; CHECK: [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF |
| ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 |
| ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<3 x s32>) |
| ; CHECK: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>) |
| ; CHECK: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[UV]](s32), [[UV3]] |
| ; CHECK: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[UV1]](s32), [[UV4]] |
| ; CHECK: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[UV2]](s32), [[UV5]] |
| ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s1>) = G_BUILD_VECTOR [[FCMP]](s1), [[FCMP1]](s1), [[FCMP2]](s1) |
| ; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s1>) |
| %0:_(<3 x s32>) = G_IMPLICIT_DEF |
| %1:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2 |
| %2:_(<3 x s1>) = G_FCMP floatpred(oeq), %0, %1 |
| S_NOP 0, implicit %2 |
| ... |
| |
| --- |
| name: test_fcmp_v4s32 |
| body: | |
| bb.0.entry: |
| liveins: $vgpr0_vgpr1_vgpr2_vgpr3 |
| |
| ; CHECK-LABEL: name: test_fcmp_v4s32 |
| ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF |
| ; CHECK: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[DEF]](p1) :: (volatile load 16) |
| ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 |
| ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<4 x s32>) |
| ; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>) |
| ; CHECK: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[UV]](s32), [[UV4]] |
| ; CHECK: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[UV1]](s32), [[UV5]] |
| ; CHECK: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[UV2]](s32), [[UV6]] |
| ; CHECK: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[UV3]](s32), [[UV7]] |
| ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s1>) = G_BUILD_VECTOR [[FCMP]](s1), [[FCMP1]](s1), [[FCMP2]](s1), [[FCMP3]](s1) |
| ; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<4 x s1>) |
| %0:_(p1) = G_IMPLICIT_DEF |
| %1:_(<4 x s32>) = G_LOAD %0 :: (volatile load 16) |
| %2:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 |
| %3:_(<4 x s1>) = G_FCMP floatpred(oeq) , %1, %2 |
| S_NOP 0, implicit %3 |
| |
| ... |