commit 2b0c82a99f57f3314f5a97692791a9e5767bdf72
author Zinovy Nis <zinovy.nis@gmail.com> Sun Oct 20 20:01:16 2019 +0000
committer Zinovy Nis <zinovy.nis@gmail.com> Sun Oct 20 20:01:16 2019 +0000
tree 906d04e635a6afdba44ff3eb54c2c7a9f588a8af
parent 3ab0cb15c09776e346e9983492952d3aed6c4276

Fix buildbot error in SIRegisterInfo.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375373 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/AMDGPU/SIRegisterInfo.cpp

diff --git a/lib/Target/AMDGPU/SIRegisterInfo.cpp b/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 7ff5b68..f58bc30 100644
--- a/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -376,9 +376,6 @@
 
 void SIRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
                                        int64_t Offset) const {
-
-  MachineBasicBlock *MBB = MI.getParent();
-  MachineFunction *MF = MBB->getParent();
   const SIInstrInfo *TII = ST.getInstrInfo();
 
 #ifndef NDEBUG
@@ -395,6 +392,10 @@
 #endif
 
   MachineOperand *FIOp = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr);
+#ifndef NDEBUG
+  MachineBasicBlock *MBB = MI.getParent();
+  MachineFunction *MF = MBB->getParent();
+#endif
   assert(FIOp && FIOp->isFI() && "frame index must be address operand");
   assert(TII->isMUBUF(MI));
   assert(TII->getNamedOperand(MI, AMDGPU::OpName::soffset)->getReg() ==