[AMDGPU][MC][DOC] A fix for build failure in r349370
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349375 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/docs/AMDGPU/gfx7_attr.rst b/docs/AMDGPU/gfx7_attr.rst
index 13096f2..219b774 100644
--- a/docs/AMDGPU/gfx7_attr.rst
+++ b/docs/AMDGPU/gfx7_attr.rst
@@ -23,7 +23,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
v_interp_p1_f32 v1, v0, attr0.x
v_interp_p1_f32 v1, v0, attr32.w
diff --git a/docs/AMDGPU/gfx7_hwreg.rst b/docs/AMDGPU/gfx7_hwreg.rst
index 1b0c542..1e2d964 100644
--- a/docs/AMDGPU/gfx7_hwreg.rst
+++ b/docs/AMDGPU/gfx7_hwreg.rst
@@ -51,7 +51,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
s_getreg_b32 s2, 0x6
s_getreg_b32 s2, hwreg(15)
diff --git a/docs/AMDGPU/gfx7_label.rst b/docs/AMDGPU/gfx7_label.rst
index e0153e7..ed2f3a4 100644
--- a/docs/AMDGPU/gfx7_label.rst
+++ b/docs/AMDGPU/gfx7_label.rst
@@ -20,7 +20,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
offset = 30
s_branch loop_end
diff --git a/docs/AMDGPU/gfx7_msg.rst b/docs/AMDGPU/gfx7_msg.rst
index ad5fd7f..5476053 100644
--- a/docs/AMDGPU/gfx7_msg.rst
+++ b/docs/AMDGPU/gfx7_msg.rst
@@ -60,7 +60,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
s_sendmsg 0x12
s_sendmsg sendmsg(MSG_INTERRUPT)
diff --git a/docs/AMDGPU/gfx7_src_exp.rst b/docs/AMDGPU/gfx7_src_exp.rst
index 6d155a5..32f71a8 100644
--- a/docs/AMDGPU/gfx7_src_exp.rst
+++ b/docs/AMDGPU/gfx7_src_exp.rst
@@ -19,7 +19,7 @@
An example:
-.. code-block:: nasm
+.. parsed-literal::
exp mrtz v3, v3, off, off compr
diff --git a/docs/AMDGPU/gfx7_waitcnt.rst b/docs/AMDGPU/gfx7_waitcnt.rst
index c89a320..3f5e07d 100644
--- a/docs/AMDGPU/gfx7_waitcnt.rst
+++ b/docs/AMDGPU/gfx7_waitcnt.rst
@@ -44,7 +44,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
s_waitcnt 0
s_waitcnt vmcnt(1)
diff --git a/docs/AMDGPU/gfx8_attr.rst b/docs/AMDGPU/gfx8_attr.rst
index 3f28033..12fa2cd 100644
--- a/docs/AMDGPU/gfx8_attr.rst
+++ b/docs/AMDGPU/gfx8_attr.rst
@@ -23,7 +23,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
v_interp_p1_f32 v1, v0, attr0.x
v_interp_p1_f32 v1, v0, attr32.w
diff --git a/docs/AMDGPU/gfx8_hwreg.rst b/docs/AMDGPU/gfx8_hwreg.rst
index d9b4299..ffa1ea5 100644
--- a/docs/AMDGPU/gfx8_hwreg.rst
+++ b/docs/AMDGPU/gfx8_hwreg.rst
@@ -51,7 +51,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
s_getreg_b32 s2, 0x6
s_getreg_b32 s2, hwreg(15)
diff --git a/docs/AMDGPU/gfx8_label.rst b/docs/AMDGPU/gfx8_label.rst
index af63ad9..99e384e 100644
--- a/docs/AMDGPU/gfx8_label.rst
+++ b/docs/AMDGPU/gfx8_label.rst
@@ -20,7 +20,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
offset = 30
s_branch loop_end
diff --git a/docs/AMDGPU/gfx8_msg.rst b/docs/AMDGPU/gfx8_msg.rst
index 8140bc2..313d8e6 100644
--- a/docs/AMDGPU/gfx8_msg.rst
+++ b/docs/AMDGPU/gfx8_msg.rst
@@ -60,7 +60,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
s_sendmsg 0x12
s_sendmsg sendmsg(MSG_INTERRUPT)
diff --git a/docs/AMDGPU/gfx8_src_exp.rst b/docs/AMDGPU/gfx8_src_exp.rst
index 92340c5..10449b4 100644
--- a/docs/AMDGPU/gfx8_src_exp.rst
+++ b/docs/AMDGPU/gfx8_src_exp.rst
@@ -19,7 +19,7 @@
An example:
-.. code-block:: nasm
+.. parsed-literal::
exp mrtz v3, v3, off, off compr
diff --git a/docs/AMDGPU/gfx8_waitcnt.rst b/docs/AMDGPU/gfx8_waitcnt.rst
index d164788..4bad594 100644
--- a/docs/AMDGPU/gfx8_waitcnt.rst
+++ b/docs/AMDGPU/gfx8_waitcnt.rst
@@ -44,7 +44,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
s_waitcnt 0
s_waitcnt vmcnt(1)
diff --git a/docs/AMDGPU/gfx9_attr.rst b/docs/AMDGPU/gfx9_attr.rst
index c69589f..faffcc7 100644
--- a/docs/AMDGPU/gfx9_attr.rst
+++ b/docs/AMDGPU/gfx9_attr.rst
@@ -23,7 +23,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
v_interp_p1_f32 v1, v0, attr0.x
v_interp_p1_f32 v1, v0, attr32.w
diff --git a/docs/AMDGPU/gfx9_hwreg.rst b/docs/AMDGPU/gfx9_hwreg.rst
index cecba1e..7ebb38b 100644
--- a/docs/AMDGPU/gfx9_hwreg.rst
+++ b/docs/AMDGPU/gfx9_hwreg.rst
@@ -52,7 +52,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
s_getreg_b32 s2, 0x6
s_getreg_b32 s2, hwreg(15)
diff --git a/docs/AMDGPU/gfx9_label.rst b/docs/AMDGPU/gfx9_label.rst
index 09fde5e..3277172 100644
--- a/docs/AMDGPU/gfx9_label.rst
+++ b/docs/AMDGPU/gfx9_label.rst
@@ -20,7 +20,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
offset = 30
s_branch loop_end
diff --git a/docs/AMDGPU/gfx9_msg.rst b/docs/AMDGPU/gfx9_msg.rst
index 41cd7da..f18cff4 100644
--- a/docs/AMDGPU/gfx9_msg.rst
+++ b/docs/AMDGPU/gfx9_msg.rst
@@ -60,7 +60,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
s_sendmsg 0x12
s_sendmsg sendmsg(MSG_INTERRUPT)
diff --git a/docs/AMDGPU/gfx9_src_exp.rst b/docs/AMDGPU/gfx9_src_exp.rst
index 71eaac0..91a5d53 100644
--- a/docs/AMDGPU/gfx9_src_exp.rst
+++ b/docs/AMDGPU/gfx9_src_exp.rst
@@ -19,7 +19,7 @@
An example:
-.. code-block:: nasm
+.. parsed-literal::
exp mrtz v3, v3, off, off compr
diff --git a/docs/AMDGPU/gfx9_waitcnt.rst b/docs/AMDGPU/gfx9_waitcnt.rst
index 5f755fc..015a51a 100644
--- a/docs/AMDGPU/gfx9_waitcnt.rst
+++ b/docs/AMDGPU/gfx9_waitcnt.rst
@@ -45,7 +45,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
s_waitcnt 0
s_waitcnt vmcnt(1)
diff --git a/docs/AMDGPUInstructionNotation.rst b/docs/AMDGPUInstructionNotation.rst
index a2b617c2..2b41d5b 100644
--- a/docs/AMDGPUInstructionNotation.rst
+++ b/docs/AMDGPUInstructionNotation.rst
@@ -81,7 +81,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
src1:m // src1 operand may be used with operand modifiers
vdata:dst // vdata operand may be used as both source and destination
diff --git a/docs/AMDGPUInstructionSyntax.rst b/docs/AMDGPUInstructionSyntax.rst
index 3beb1c3..90ad54a 100644
--- a/docs/AMDGPUInstructionSyntax.rst
+++ b/docs/AMDGPUInstructionSyntax.rst
@@ -90,21 +90,21 @@
Examples of instructions with different types of source and destination operands:
-.. code-block:: nasm
+.. parsed-literal::
s_bcnt0_i32_b64
v_cvt_f32_u32
Examples of instructions with one data type:
-.. code-block:: nasm
+.. parsed-literal::
v_max3_f32
v_max3_i16
Examples of instructions which operate with packed data:
-.. code-block:: nasm
+.. parsed-literal::
v_pk_add_u16
v_pk_add_i16
@@ -112,7 +112,7 @@
Examples of typeless instructions which operate on b128 data:
-.. code-block:: nasm
+.. parsed-literal::
buffer_store_dwordx4
flat_load_dwordx4
diff --git a/docs/AMDGPUModifierSyntax.rst b/docs/AMDGPUModifierSyntax.rst
index bc2ddd0..e2b8bb3 100644
--- a/docs/AMDGPUModifierSyntax.rst
+++ b/docs/AMDGPUModifierSyntax.rst
@@ -43,7 +43,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
offset:255
offset:0xff
@@ -66,7 +66,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
offset:65535
offset:0xffff
@@ -133,7 +133,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
offset:255
offset:0xffff
@@ -221,7 +221,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
offset:4095
offset:0xff
@@ -244,7 +244,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
offset:-4000
offset:0x10
@@ -309,7 +309,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
dmask:0xf
dmask:0b1111
@@ -559,7 +559,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
offset:0
offset:0x10
@@ -674,7 +674,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
quad_perm:[0, 1, 2, 3]
row_shl:3
@@ -700,7 +700,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
row_mask:0xf
row_mask:0b1010
@@ -727,7 +727,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
bank_mask:0x3
bank_mask:0b0011
@@ -879,7 +879,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
sext(v4)
sext(v255)
@@ -915,7 +915,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
op_sel:[0,0]
op_sel:[0,1]
@@ -994,10 +994,10 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
abs(v36)
- |v36|
+ \|v36|
.. _amdgpu_synid_neg:
@@ -1016,7 +1016,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
neg(v[0])
-v4
@@ -1055,7 +1055,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
op_sel:[0,0]
op_sel:[0,1,0]
@@ -1084,7 +1084,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
op_sel_hi:[0,0]
op_sel_hi:[0,0,1]
@@ -1118,7 +1118,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
neg_lo:[0]
neg_lo:[0,1]
@@ -1152,7 +1152,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
neg_hi:[1,0]
neg_hi:[0,1,1]
@@ -1200,7 +1200,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
op_sel:[0,1]
@@ -1228,7 +1228,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
op_sel_hi:[1,1,1]
diff --git a/docs/AMDGPUOperandSyntax.rst b/docs/AMDGPUOperandSyntax.rst
index e415452..5f5d822 100644
--- a/docs/AMDGPUOperandSyntax.rst
+++ b/docs/AMDGPUOperandSyntax.rst
@@ -63,7 +63,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
v255
v[0]
@@ -127,7 +127,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
s0
s[0]
@@ -141,7 +141,7 @@
Examples of *scalar* registers with an invalid alignment:
-.. code-block:: nasm
+.. parsed-literal::
s[1:2]
s[2:5]
@@ -210,7 +210,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
ttmp0
ttmp[0]
@@ -224,7 +224,7 @@
Examples of *ttmp* registers with an invalid alignment:
-.. code-block:: nasm
+.. parsed-literal::
ttmp[1:2]
ttmp[2:5]
@@ -645,7 +645,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
-1234
0b1010
@@ -671,7 +671,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
-1.234
234e2
@@ -700,7 +700,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
x = -1
y = x + 10
@@ -719,7 +719,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
y = x + 10 // x is not yet defined. Undefined symbols are assumed to be PC-relative.
z = .
@@ -736,7 +736,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
x = 0.1 // x is assigned an integer 4591870180066957722 which is a binary representation of 0.1.
y = x + x // y is a sum of two integer values; it is not equal to 0.2!
@@ -897,7 +897,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
// GFX9
@@ -920,7 +920,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
// GFX9
@@ -969,7 +969,7 @@
Examples of valid literals:
-.. code-block:: nasm
+.. parsed-literal::
// GFX9
@@ -983,7 +983,7 @@
Examples of invalid literals:
-.. code-block:: nasm
+.. parsed-literal::
// GFX9
@@ -1021,7 +1021,7 @@
Examples of valid literals:
-.. code-block:: nasm
+.. parsed-literal::
// GFX9
@@ -1033,7 +1033,7 @@
Examples of invalid literals:
-.. code-block:: nasm
+.. parsed-literal::
// GFX9
@@ -1052,7 +1052,7 @@
Examples:
-.. code-block:: nasm
+.. parsed-literal::
// GFX9
