| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=regbankselect %s -o - | FileCheck %s |
| |
| # The following should hold here: |
| # |
| # 1) The first and second operands of G_INSERT_VECTOR_ELT should be FPRs since |
| # they are vectors. |
| # |
| # 2) The third operand should be on the register bank given in the test name |
| # (e.g, v4s32_fpr). AArch64 supports native inserts of GPRs, so we need to |
| # preserve that. |
| # |
| # 3) The fourth operand should be a GPR, since it's a constant. |
| |
| name: v4s32_fpr |
| alignment: 2 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $q1, $s0 |
| |
| ; CHECK-LABEL: name: v4s32_fpr |
| ; CHECK: liveins: $q1, $s0 |
| ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0 |
| ; CHECK: [[COPY1:%[0-9]+]]:fpr(<4 x s32>) = COPY $q1 |
| ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1 |
| ; CHECK: [[IVEC:%[0-9]+]]:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s32) |
| ; CHECK: $q0 = COPY [[IVEC]](<4 x s32>) |
| ; CHECK: RET_ReallyLR implicit $q0 |
| %0:_(s32) = COPY $s0 |
| %1:_(<4 x s32>) = COPY $q1 |
| %3:_(s32) = G_CONSTANT i32 1 |
| %2:_(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32) |
| $q0 = COPY %2(<4 x s32>) |
| RET_ReallyLR implicit $q0 |
| |
| ... |
| --- |
| name: v4s32_gpr |
| alignment: 2 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $q0, $w0 |
| |
| ; CHECK-LABEL: name: v4s32_gpr |
| ; CHECK: liveins: $q0, $w0 |
| ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0 |
| ; CHECK: [[COPY1:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0 |
| ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1 |
| ; CHECK: [[IVEC:%[0-9]+]]:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s32) |
| ; CHECK: $q0 = COPY [[IVEC]](<4 x s32>) |
| ; CHECK: RET_ReallyLR implicit $q0 |
| %0:_(s32) = COPY $w0 |
| %1:_(<4 x s32>) = COPY $q0 |
| %3:_(s32) = G_CONSTANT i32 1 |
| %2:_(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32) |
| $q0 = COPY %2(<4 x s32>) |
| RET_ReallyLR implicit $q0 |
| |
| ... |
| --- |
| name: v2s64_fpr |
| alignment: 2 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $d0, $q1 |
| |
| ; CHECK-LABEL: name: v2s64_fpr |
| ; CHECK: liveins: $d0, $q1 |
| ; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0 |
| ; CHECK: [[COPY1:%[0-9]+]]:fpr(<2 x s64>) = COPY $q1 |
| ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1 |
| ; CHECK: [[IVEC:%[0-9]+]]:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s64), [[C]](s32) |
| ; CHECK: $q0 = COPY [[IVEC]](<2 x s64>) |
| ; CHECK: RET_ReallyLR implicit $q0 |
| %0:_(s64) = COPY $d0 |
| %1:_(<2 x s64>) = COPY $q1 |
| %3:_(s32) = G_CONSTANT i32 1 |
| %2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s32) |
| $q0 = COPY %2(<2 x s64>) |
| RET_ReallyLR implicit $q0 |
| |
| ... |
| --- |
| name: v2s64_gpr |
| alignment: 2 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $q0, $x0 |
| |
| ; CHECK-LABEL: name: v2s64_gpr |
| ; CHECK: liveins: $q0, $x0 |
| ; CHECK: [[COPY:%[0-9]+]]:gpr(s64) = COPY $x0 |
| ; CHECK: [[COPY1:%[0-9]+]]:fpr(<2 x s64>) = COPY $q0 |
| ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0 |
| ; CHECK: [[IVEC:%[0-9]+]]:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s64), [[C]](s32) |
| ; CHECK: $q0 = COPY [[IVEC]](<2 x s64>) |
| ; CHECK: RET_ReallyLR implicit $q0 |
| %0:_(s64) = COPY $x0 |
| %1:_(<2 x s64>) = COPY $q0 |
| %3:_(s32) = G_CONSTANT i32 0 |
| %2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s32) |
| $q0 = COPY %2(<2 x s64>) |
| RET_ReallyLR implicit $q0 |
| |
| ... |
| --- |
| name: v2s32_fpr |
| alignment: 2 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $d1, $s0 |
| |
| ; CHECK-LABEL: name: v2s32_fpr |
| ; CHECK: liveins: $d1, $s0 |
| ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0 |
| ; CHECK: [[COPY1:%[0-9]+]]:fpr(<2 x s32>) = COPY $d1 |
| ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1 |
| ; CHECK: [[IVEC:%[0-9]+]]:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s32) |
| ; CHECK: $d0 = COPY [[IVEC]](<2 x s32>) |
| ; CHECK: RET_ReallyLR implicit $d0 |
| %0:_(s32) = COPY $s0 |
| %1:_(<2 x s32>) = COPY $d1 |
| %3:_(s32) = G_CONSTANT i32 1 |
| %2:_(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32) |
| $d0 = COPY %2(<2 x s32>) |
| RET_ReallyLR implicit $d0 |
| |
| ... |
| --- |
| name: v2s32_gpr |
| alignment: 2 |
| legalized: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $d0, $w0 |
| |
| ; CHECK-LABEL: name: v2s32_gpr |
| ; CHECK: liveins: $d0, $w0 |
| ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0 |
| ; CHECK: [[COPY1:%[0-9]+]]:fpr(<2 x s32>) = COPY $d0 |
| ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1 |
| ; CHECK: [[IVEC:%[0-9]+]]:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s32) |
| ; CHECK: $d0 = COPY [[IVEC]](<2 x s32>) |
| ; CHECK: RET_ReallyLR implicit $d0 |
| %0:_(s32) = COPY $w0 |
| %1:_(<2 x s32>) = COPY $d0 |
| %3:_(s32) = G_CONSTANT i32 1 |
| %2:_(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32) |
| $d0 = COPY %2(<2 x s32>) |
| RET_ReallyLR implicit $d0 |
| |
| ... |