| //===-- RISCVAsmBackend.h - RISCV Assembler Backend -----------------------===// |
| // |
| // The LLVM Compiler Infrastructure |
| // |
| // This file is distributed under the University of Illinois Open Source |
| // License. See LICENSE.TXT for details. |
| // |
| //===----------------------------------------------------------------------===// |
| |
| #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVASMBACKEND_H |
| #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVASMBACKEND_H |
| |
| #include "MCTargetDesc/RISCVFixupKinds.h" |
| #include "MCTargetDesc/RISCVMCTargetDesc.h" |
| #include "llvm/MC/MCAsmBackend.h" |
| #include "llvm/MC/MCFixupKindInfo.h" |
| #include "llvm/MC/MCSubtargetInfo.h" |
| |
| namespace llvm { |
| class MCAssembler; |
| class MCObjectTargetWriter; |
| class raw_ostream; |
| |
| class RISCVAsmBackend : public MCAsmBackend { |
| const MCSubtargetInfo &STI; |
| uint8_t OSABI; |
| bool Is64Bit; |
| bool ForceRelocs = false; |
| |
| public: |
| RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit) |
| : MCAsmBackend(support::little), STI(STI), OSABI(OSABI), |
| Is64Bit(Is64Bit) {} |
| ~RISCVAsmBackend() override {} |
| |
| void setForceRelocs() { ForceRelocs = true; } |
| |
| // Generate diff expression relocations if the relax feature is enabled or had |
| // previously been enabled, otherwise it is safe for the assembler to |
| // calculate these internally. |
| bool requiresDiffExpressionRelocations() const override { |
| return STI.getFeatureBits()[RISCV::FeatureRelax] || ForceRelocs; |
| } |
| void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, |
| const MCValue &Target, MutableArrayRef<char> Data, |
| uint64_t Value, bool IsResolved, |
| const MCSubtargetInfo *STI) const override; |
| |
| std::unique_ptr<MCObjectTargetWriter> |
| createObjectTargetWriter() const override; |
| |
| bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, |
| const MCValue &Target) override; |
| |
| bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, |
| const MCRelaxableFragment *DF, |
| const MCAsmLayout &Layout) const override { |
| llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced"); |
| } |
| |
| bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved, |
| uint64_t Value, |
| const MCRelaxableFragment *DF, |
| const MCAsmLayout &Layout, |
| const bool WasForced) const override; |
| |
| unsigned getNumFixupKinds() const override { |
| return RISCV::NumTargetFixupKinds; |
| } |
| |
| const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override { |
| const static MCFixupKindInfo Infos[] = { |
| // This table *must* be in the order that the fixup_* kinds are defined in |
| // RISCVFixupKinds.h. |
| // |
| // name offset bits flags |
| { "fixup_riscv_hi20", 12, 20, 0 }, |
| { "fixup_riscv_lo12_i", 20, 12, 0 }, |
| { "fixup_riscv_lo12_s", 0, 32, 0 }, |
| { "fixup_riscv_pcrel_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel }, |
| { "fixup_riscv_pcrel_lo12_i", 20, 12, MCFixupKindInfo::FKF_IsPCRel }, |
| { "fixup_riscv_pcrel_lo12_s", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, |
| { "fixup_riscv_jal", 12, 20, MCFixupKindInfo::FKF_IsPCRel }, |
| { "fixup_riscv_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, |
| { "fixup_riscv_rvc_jump", 2, 11, MCFixupKindInfo::FKF_IsPCRel }, |
| { "fixup_riscv_rvc_branch", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, |
| { "fixup_riscv_call", 0, 64, MCFixupKindInfo::FKF_IsPCRel }, |
| { "fixup_riscv_relax", 0, 0, 0 } |
| }; |
| static_assert((array_lengthof(Infos)) == RISCV::NumTargetFixupKinds, |
| "Not all fixup kinds added to Infos array"); |
| |
| if (Kind < FirstTargetFixupKind) |
| return MCAsmBackend::getFixupKindInfo(Kind); |
| |
| assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && |
| "Invalid kind!"); |
| return Infos[Kind - FirstTargetFixupKind]; |
| } |
| |
| bool mayNeedRelaxation(const MCInst &Inst, |
| const MCSubtargetInfo &STI) const override; |
| unsigned getRelaxedOpcode(unsigned Op) const; |
| |
| void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, |
| MCInst &Res) const override; |
| |
| |
| bool writeNopData(raw_ostream &OS, uint64_t Count) const override; |
| }; |
| } |
| |
| #endif |