| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mtriple=thumbv7m-none-eabi -run-pass=arm-cp-islands -o - %s | FileCheck %s |
| |
| --- | |
| define i32* @test_simple(i32* %x, i32 %y) { ret i32* %x } |
| define i32* @test_notfirst(i32* %x, i32 %y) { ret i32* %x } |
| define i32* @test_redefined(i32* %x, i32 %y) { ret i32* %x } |
| define i32* @test_notredefined(i32* %x, i32 %y) { ret i32* %x } |
| define i32* @test_notcmp(i32* %x, i32 %y) { ret i32* %x } |
| define i32* @test_killflag_1(i32* %x, i32 %y) { ret i32* %x } |
| define i32* @test_killflag_2(i32* %x, i32 %y) { ret i32* %x } |
| define i32* @test_cpsr(i32* %x, i32 %y) { ret i32* %x } |
| |
| declare dso_local i32 @c(i32 %x) |
| ... |
| --- |
| name: test_simple |
| tracksRegLiveness: true |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| body: | |
| ; CHECK-LABEL: name: test_simple |
| ; CHECK: bb.0: |
| ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) |
| ; CHECK: tCBZ $r0, %bb.2 |
| ; CHECK: bb.1: |
| ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) |
| ; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 |
| ; CHECK: bb.2: |
| ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg |
| ; CHECK: tBX_RET 14, $noreg, implicit killed $r0 |
| bb.0: |
| successors: %bb.1(0x30000000), %bb.2(0x50000000) |
| liveins: $r0, $r1 |
| |
| tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr |
| t2Bcc %bb.1, 0, killed $cpsr |
| |
| bb.2: |
| liveins: $r0 |
| |
| renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) |
| tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 |
| |
| bb.1: |
| $r0, dead $cpsr = tMOVi8 0, 14, $noreg |
| tBX_RET 14, $noreg, implicit killed $r0 |
| |
| ... |
| --- |
| name: test_notfirst |
| tracksRegLiveness: true |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| body: | |
| ; CHECK-LABEL: name: test_notfirst |
| ; CHECK: bb.0: |
| ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) |
| ; CHECK: renamable $r0, $cpsr = tADDrr killed renamable $r0, renamable $r1, 14, $noreg |
| ; CHECK: renamable $r1 = t2ADDrs renamable $r0, killed renamable $r1, 18, 14, $noreg, $noreg |
| ; CHECK: tCBZ $r0, %bb.2 |
| ; CHECK: bb.1: |
| ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) |
| ; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 |
| ; CHECK: bb.2: |
| ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg |
| ; CHECK: tBX_RET 14, $noreg, implicit killed $r0 |
| bb.0: |
| successors: %bb.1(0x30000000), %bb.2(0x50000000) |
| liveins: $r0, $r1 |
| |
| renamable $r0, $cpsr = tADDrr killed renamable $r0, renamable $r1, 14, $noreg |
| tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr |
| renamable $r1 = t2ADDrs renamable $r0, killed renamable $r1, 18, 14, $noreg, $noreg |
| t2Bcc %bb.1, 0, killed $cpsr |
| |
| bb.2: |
| liveins: $r0 |
| |
| renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) |
| tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 |
| |
| bb.1: |
| $r0, dead $cpsr = tMOVi8 0, 14, $noreg |
| tBX_RET 14, $noreg, implicit killed $r0 |
| |
| ... |
| --- |
| name: test_redefined |
| tracksRegLiveness: true |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| body: | |
| ; CHECK-LABEL: name: test_redefined |
| ; CHECK: bb.0: |
| ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) |
| ; CHECK: tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr |
| ; CHECK: renamable $r0 = t2ADDrs killed renamable $r0, killed renamable $r1, 18, 14, $noreg, $noreg |
| ; CHECK: tBcc %bb.2, 0, killed $cpsr |
| ; CHECK: bb.1: |
| ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) |
| ; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 |
| ; CHECK: bb.2: |
| ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg |
| ; CHECK: tBX_RET 14, $noreg, implicit killed $r0 |
| bb.0: |
| successors: %bb.1(0x30000000), %bb.2(0x50000000) |
| liveins: $r0, $r1 |
| |
| tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr |
| renamable $r0 = t2ADDrs killed renamable $r0, killed renamable $r1, 18, 14, $noreg, $noreg |
| t2Bcc %bb.1, 0, killed $cpsr |
| |
| bb.2: |
| liveins: $r0 |
| |
| renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) |
| tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 |
| |
| bb.1: |
| $r0, dead $cpsr = tMOVi8 0, 14, $noreg |
| tBX_RET 14, $noreg, implicit killed $r0 |
| |
| ... |
| --- |
| name: test_notredefined |
| tracksRegLiveness: true |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| body: | |
| ; CHECK-LABEL: name: test_notredefined |
| ; CHECK: bb.0: |
| ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) |
| ; CHECK: renamable $r1 = t2ADDrs renamable $r0, killed renamable $r1, 18, 14, $noreg, $noreg |
| ; CHECK: tCBZ $r0, %bb.2 |
| ; CHECK: bb.1: |
| ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) |
| ; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 |
| ; CHECK: bb.2: |
| ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg |
| ; CHECK: tBX_RET 14, $noreg, implicit killed $r0 |
| bb.0: |
| successors: %bb.1(0x30000000), %bb.2(0x50000000) |
| liveins: $r0, $r1 |
| |
| tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr |
| renamable $r1 = t2ADDrs renamable $r0, killed renamable $r1, 18, 14, $noreg, $noreg |
| t2Bcc %bb.1, 0, killed $cpsr |
| |
| bb.2: |
| liveins: $r0 |
| |
| renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) |
| tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 |
| |
| bb.1: |
| $r0, dead $cpsr = tMOVi8 0, 14, $noreg |
| tBX_RET 14, $noreg, implicit killed $r0 |
| |
| ... |
| --- |
| name: test_notcmp |
| tracksRegLiveness: true |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| body: | |
| ; CHECK-LABEL: name: test_notcmp |
| ; CHECK: bb.0: |
| ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) |
| ; CHECK: tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr |
| ; CHECK: renamable $r1, $cpsr = tADDrr renamable $r0, killed renamable $r1, 14, $noreg |
| ; CHECK: tBcc %bb.2, 0, killed $cpsr |
| ; CHECK: bb.1: |
| ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) |
| ; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 |
| ; CHECK: bb.2: |
| ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg |
| ; CHECK: tBX_RET 14, $noreg, implicit killed $r0 |
| bb.0: |
| successors: %bb.1(0x30000000), %bb.2(0x50000000) |
| liveins: $r0, $r1 |
| |
| tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr |
| renamable $r1, $cpsr = tADDrr renamable $r0, killed renamable $r1, 14, $noreg |
| t2Bcc %bb.1, 0, killed $cpsr |
| |
| bb.2: |
| liveins: $r0 |
| |
| renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) |
| tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 |
| |
| bb.1: |
| $r0, dead $cpsr = tMOVi8 0, 14, $noreg |
| tBX_RET 14, $noreg, implicit killed $r0 |
| |
| ... |
| --- |
| name: test_killflag_1 |
| tracksRegLiveness: true |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| body: | |
| ; CHECK-LABEL: name: test_killflag_1 |
| ; CHECK: bb.0: |
| ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) |
| ; CHECK: renamable $r0 = t2ADDrs killed renamable $r0, killed renamable $r0, 18, 14, $noreg, $noreg |
| ; CHECK: tCBZ killed $r1, %bb.2 |
| ; CHECK: bb.1: |
| ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) |
| ; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 |
| ; CHECK: bb.2: |
| ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg |
| ; CHECK: tBX_RET 14, $noreg, implicit killed $r0 |
| bb.0: |
| successors: %bb.1(0x30000000), %bb.2(0x50000000) |
| liveins: $r0, $r1 |
| |
| tCMPi8 killed renamable $r1, 0, 14, $noreg, implicit-def $cpsr |
| renamable $r0 = t2ADDrs killed renamable $r0, killed renamable $r0, 18, 14, $noreg, $noreg |
| t2Bcc %bb.1, 0, killed $cpsr |
| |
| bb.2: |
| liveins: $r0 |
| |
| renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) |
| tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 |
| |
| bb.1: |
| $r0, dead $cpsr = tMOVi8 0, 14, $noreg |
| tBX_RET 14, $noreg, implicit killed $r0 |
| |
| ... |
| --- |
| name: test_killflag_2 |
| tracksRegLiveness: true |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| body: | |
| ; CHECK-LABEL: name: test_killflag_2 |
| ; CHECK: bb.0: |
| ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) |
| ; CHECK: renamable $r0 = t2ADDrs renamable $r1, killed renamable $r0, 18, 14, $noreg, $noreg |
| ; CHECK: tCBZ killed $r1, %bb.2 |
| ; CHECK: bb.1: |
| ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) |
| ; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 |
| ; CHECK: bb.2: |
| ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg |
| ; CHECK: tBX_RET 14, $noreg, implicit killed $r0 |
| bb.0: |
| successors: %bb.1(0x30000000), %bb.2(0x50000000) |
| liveins: $r0, $r1 |
| |
| tCMPi8 renamable $r1, 0, 14, $noreg, implicit-def $cpsr |
| renamable $r0 = t2ADDrs killed renamable $r1, killed renamable $r0, 18, 14, $noreg, $noreg |
| t2Bcc %bb.1, 0, killed $cpsr |
| |
| bb.2: |
| liveins: $r0 |
| |
| renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) |
| tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 |
| |
| bb.1: |
| $r0, dead $cpsr = tMOVi8 0, 14, $noreg |
| tBX_RET 14, $noreg, implicit killed $r0 |
| |
| ... |
| --- |
| name: test_cpsr |
| tracksRegLiveness: true |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| body: | |
| ; CHECK-LABEL: name: test_cpsr |
| ; CHECK: bb.0: |
| ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) |
| ; CHECK: tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr |
| ; CHECK: t2IT 0, 8, implicit-def $itstate |
| ; CHECK: renamable $r1 = t2ADDri killed renamable $r1, 1, 1, $cpsr, $noreg, implicit killed $itstate |
| ; CHECK: tBcc %bb.2, 0, killed $cpsr |
| ; CHECK: bb.1: |
| ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) |
| ; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 |
| ; CHECK: bb.2: |
| ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg |
| ; CHECK: tBX_RET 14, $noreg, implicit killed $r0 |
| bb.0: |
| successors: %bb.1(0x30000000), %bb.2(0x50000000) |
| liveins: $r0, $r1 |
| |
| tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr |
| t2IT 0, 8, implicit-def $itstate |
| renamable $r1 = t2ADDri killed renamable $r1, 1, 1, $cpsr, $noreg, implicit killed $itstate |
| t2Bcc %bb.1, 0, killed $cpsr |
| |
| bb.2: |
| liveins: $r0 |
| |
| renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) |
| tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 |
| |
| bb.1: |
| $r0, dead $cpsr = tMOVi8 0, 14, $noreg |
| tBX_RET 14, $noreg, implicit killed $r0 |
| |
| ... |
| |