[AMDGPU][MC][CODEOBJECT] Added predefined symbols to access GPU minor and stepping numbers
Added the following Code Object v3 symbols:
.amdgcn.gfx_generation_minor
.amdgcn.gfx_generation_stepping
Reviewers: artem.tamazov, kzhuravl
Differential Revision: https://reviews.llvm.org/D57826
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353515 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/docs/AMDGPUUsage.rst b/docs/AMDGPUUsage.rst
index c60d60a..7963543 100644
--- a/docs/AMDGPUUsage.rst
+++ b/docs/AMDGPUUsage.rst
@@ -4875,11 +4875,27 @@
.amdgcn.gfx_generation_number
+++++++++++++++++++++++++++++
-Set to the GFX generation number of the target being assembled for. For
+Set to the GFX major generation number of the target being assembled for. For
example, when assembling for a "GFX9" target this will be set to the integer
-value "9". The possible GFX generation numbers are presented in
+value "9". The possible GFX major generation numbers are presented in
:ref:`amdgpu-processors`.
+.amdgcn.gfx_generation_minor
+++++++++++++++++++++++++++++
+
+Set to the GFX minor generation number of the target being assembled for. For
+example, when assembling for a "GFX810" target this will be set to the integer
+value "1". The possible GFX minor generation numbers are presented in
+:ref:`amdgpu-processors`.
+
+.amdgcn.gfx_generation_stepping
++++++++++++++++++++++++++++++++
+
+Set to the GFX stepping generation number of the target being assembled for.
+For example, when assembling for a "GFX704" target this will be set to the
+integer value "4". The possible GFX stepping generation numbers are presented
+in :ref:`amdgpu-processors`.
+
.amdgcn.next_free_vgpr
++++++++++++++++++++++
diff --git a/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 130f0cf..89c0d48 100644
--- a/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -923,6 +923,10 @@
MCSymbol *Sym =
Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_number"));
Sym->setVariableValue(MCConstantExpr::create(ISA.Major, Ctx));
+ Sym = Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_minor"));
+ Sym->setVariableValue(MCConstantExpr::create(ISA.Minor, Ctx));
+ Sym = Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_stepping"));
+ Sym->setVariableValue(MCConstantExpr::create(ISA.Stepping, Ctx));
} else {
MCSymbol *Sym =
Ctx.getOrCreateSymbol(Twine(".option.machine_version_major"));
diff --git a/test/MC/AMDGPU/hsa-v3.s b/test/MC/AMDGPU/hsa-v3.s
index 6adcdb8..515da88 100644
--- a/test/MC/AMDGPU/hsa-v3.s
+++ b/test/MC/AMDGPU/hsa-v3.s
@@ -1,5 +1,5 @@
-// RUN: llvm-mc -mattr=+code-object-v3 -triple amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+xnack < %s | FileCheck --check-prefix=ASM %s
-// RUN: llvm-mc -mattr=+code-object-v3 -triple amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+xnack -filetype=obj < %s > %t
+// RUN: llvm-mc -mattr=+code-object-v3 -triple amdgcn-amd-amdhsa -mcpu=gfx904 -mattr=+xnack < %s | FileCheck --check-prefix=ASM %s
+// RUN: llvm-mc -mattr=+code-object-v3 -triple amdgcn-amd-amdhsa -mcpu=gfx904 -mattr=+xnack -filetype=obj < %s > %t
// RUN: llvm-readobj -elf-output-style=GNU -sections -symbols -relocations %t | FileCheck --check-prefix=READOBJ %s
// RUN: llvm-objdump -s -j .rodata %t | FileCheck --check-prefix=OBJDUMP %s
@@ -44,8 +44,8 @@
.text
// ASM: .text
-.amdgcn_target "amdgcn-amd-amdhsa--gfx900+xnack"
-// ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx900+xnack"
+.amdgcn_target "amdgcn-amd-amdhsa--gfx904+xnack"
+// ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx904+xnack"
.p2align 8
.type minimal,@function
@@ -187,6 +187,12 @@
.byte .amdgcn.gfx_generation_number
// ASM: .byte 9
+.byte .amdgcn.gfx_generation_minor
+// ASM: .byte 0
+
+.byte .amdgcn.gfx_generation_stepping
+// ASM: .byte 4
+
.byte .amdgcn.next_free_vgpr
// ASM: .byte 0
.byte .amdgcn.next_free_sgpr
