blob: 2b730581d86166dbd45326eec7c766ef99d98521 [file] [log] [blame]
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
# RUN: llc -mtriple=x86_64-linux-gnu -regbankselect-greedy -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=GREEDY
--- |
define i8 @test_add_i8(i8 %arg1, i8 %arg2) {
%ret = add i8 %arg1, %arg2
ret i8 %ret
}
define i16 @test_add_i16(i16 %arg1, i16 %arg2) {
%ret = add i16 %arg1, %arg2
ret i16 %ret
}
define i32 @test_add_i32(i32 %arg1, i32 %arg2) {
%ret = add i32 %arg1, %arg2
ret i32 %ret
}
define i64 @test_add_i64(i64 %arg1, i64 %arg2) {
%ret = add i64 %arg1, %arg2
ret i64 %ret
}
define void @test_mul_gpr() {
ret void
}
define float @test_add_float(float %arg1, float %arg2) {
%ret = fadd float %arg1, %arg2
ret float %ret
}
define double @test_add_double(double %arg1, double %arg2) {
%ret = fadd double %arg1, %arg2
ret double %ret
}
define void @test_fsub_float() {
%ret1 = fsub float undef, undef
%ret2 = fsub double undef, undef
ret void
}
define void @test_fmul_float() {
%ret1 = fmul float undef, undef
%ret2 = fmul double undef, undef
ret void
}
define void @test_fdiv_float() {
%ret1 = fdiv float undef, undef
%ret2 = fdiv double undef, undef
ret void
}
define <4 x i32> @test_add_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) {
%ret = add <4 x i32> %arg1, %arg2
ret <4 x i32> %ret
}
define <4 x float> @test_add_v4f32(<4 x float> %arg1, <4 x float> %arg2) {
%ret = fadd <4 x float> %arg1, %arg2
ret <4 x float> %ret
}
define i8 @test_load_i8(i8* %p1) {
%r = load i8, i8* %p1
ret i8 %r
}
define i16 @test_load_i16(i16* %p1) {
%r = load i16, i16* %p1
ret i16 %r
}
define i32 @test_load_i32(i32* %p1) {
%r = load i32, i32* %p1
ret i32 %r
}
define i64 @test_load_i64(i64* %p1) {
%r = load i64, i64* %p1
ret i64 %r
}
define float @test_load_float(float* %p1) {
%r = load float, float* %p1
ret float %r
}
define double @test_load_double(double* %p1) {
%r = load double, double* %p1
ret double %r
}
define <4 x i32> @test_load_v4i32(<4 x i32>* %p1) {
%r = load <4 x i32>, <4 x i32>* %p1, align 16
ret <4 x i32> %r
}
define i32* @test_store_i32(i32 %val, i32* %p1) {
store i32 %val, i32* %p1
ret i32* %p1
}
define i64* @test_store_i64(i64 %val, i64* %p1) {
store i64 %val, i64* %p1
ret i64* %p1
}
define float* @test_store_float(float %val, float* %p1) {
store float %val, float* %p1
ret float* %p1
}
define double* @test_store_double(double %val, double* %p1) {
store double %val, double* %p1
ret double* %p1
}
define void @constInt_check() {
ret void
}
define void @trunc_check() {
ret void
}
define void @test_gep() {
%p1 = getelementptr i32, i32* undef, i32 5
%p2 = getelementptr i32, i32* undef, i64 5
ret void
}
define i1 @test_icmp_eq_i8(i8 %a, i8 %b) {
%r = icmp eq i8 %a, %b
ret i1 %r
}
define i1 @test_icmp_eq_i16(i16 %a, i16 %b) {
%r = icmp eq i16 %a, %b
ret i1 %r
}
define i1 @test_icmp_eq_i32(i32 %a, i32 %b) {
%r = icmp eq i32 %a, %b
ret i1 %r
}
define i1 @test_icmp_eq_i64(i64 %a, i64 %b) {
%r = icmp eq i64 %a, %b
ret i1 %r
}
define i8 @test_xor_i8() {
%ret = xor i8 undef, undef
ret i8 %ret
}
define i16 @test_or_i16() {
%ret = or i16 undef, undef
ret i16 %ret
}
define i32 @test_and_i32() {
%ret = and i32 undef, undef
ret i32 %ret
}
define i64 @test_and_i64() {
%ret = and i64 undef, undef
ret i64 %ret
}
@g_int = global i32 0, align 4
define i32* @test_global_ptrv() {
entry:
ret i32* @g_int
}
define i8 @test_undef() {
ret i8 undef
}
define i8 @test_undef2(i8 %a) {
%r = add i8 %a, undef
ret i8 %r
}
define float @test_undef3() {
ret float undef
}
define float @test_undef4(float %a) {
%r = fadd float %a, undef
ret float %r
}
define i32 @test_i32(i32 %a, i32 %f, i32 %t) {
entry:
%cmp = icmp sgt i32 %a, 0
br i1 %cmp, label %cond.true, label %cond.false
cond.true: ; preds = %entry
br label %cond.end
cond.false: ; preds = %entry
br label %cond.end
cond.end: ; preds = %cond.false, %cond.true
%cond = phi i32 [ %f, %cond.true ], [ %t, %cond.false ]
ret i32 %cond
}
define float @test_float(i32 %a, float %f, float %t) {
entry:
%cmp = icmp sgt i32 %a, 0
br i1 %cmp, label %cond.true, label %cond.false
cond.true: ; preds = %entry
br label %cond.end
cond.false: ; preds = %entry
br label %cond.end
cond.end: ; preds = %cond.false, %cond.true
%cond = phi float [ %f, %cond.true ], [ %t, %cond.false ]
ret float %cond
}
define double @test_fpext(float %a) {
entry:
%conv = fpext float %a to double
ret double %conv
}
define float @test_fptrunc(double %a) {
entry:
%conv = fptrunc double %a to float
ret float %conv
}
define void @test_fconstant() {
ret void
}
define float @int32_to_float(i32 %a) {
entry:
%conv = sitofp i32 %a to float
ret float %conv
}
define float @int64_to_float(i64 %a) {
entry:
%conv = sitofp i64 %a to float
ret float %conv
}
define double @int32_to_double(i32 %a) {
entry:
%conv = sitofp i32 %a to double
ret double %conv
}
define double @int64_to_double(i64 %a) {
entry:
%conv = sitofp i64 %a to double
ret double %conv
}
define signext i8 @float_to_int8(float %val) {
entry:
%conv = fptosi float %val to i8
ret i8 %conv
}
define signext i16 @float_to_int16(float %val) {
entry:
%conv = fptosi float %val to i16
ret i16 %conv
}
define i32 @float_to_int32(float %val) {
entry:
%conv = fptosi float %val to i32
ret i32 %conv
}
define i64 @float_to_int64(float %val) {
entry:
%conv = fptosi float %val to i64
ret i64 %conv
}
define signext i8 @double_to_int8(double %val) {
entry:
%conv = fptosi double %val to i8
ret i8 %conv
}
define signext i16 @double_to_int16(double %val) {
entry:
%conv = fptosi double %val to i16
ret i16 %conv
}
define i32 @double_to_int32(double %val) {
entry:
%conv = fptosi double %val to i32
ret i32 %conv
}
define i64 @double_to_int64(double %val) {
entry:
%conv = fptosi double %val to i64
ret i64 %conv
}
define i1 @fcmp_float_oeq(float %x, float %y) {
%1 = fcmp oeq float %x, %y
ret i1 %1
}
define i1 @fcmp_float_ogt(float %x, float %y) {
%1 = fcmp ogt float %x, %y
ret i1 %1
}
define i1 @fcmp_float_oge(float %x, float %y) {
%1 = fcmp oge float %x, %y
ret i1 %1
}
define i1 @fcmp_float_olt(float %x, float %y) {
%1 = fcmp olt float %x, %y
ret i1 %1
}
define i1 @fcmp_float_ole(float %x, float %y) {
%1 = fcmp ole float %x, %y
ret i1 %1
}
define i1 @fcmp_float_one(float %x, float %y) {
%1 = fcmp one float %x, %y
ret i1 %1
}
define i1 @fcmp_float_ord(float %x, float %y) {
%1 = fcmp ord float %x, %y
ret i1 %1
}
define i1 @fcmp_float_uno(float %x, float %y) {
%1 = fcmp uno float %x, %y
ret i1 %1
}
define i1 @fcmp_float_ueq(float %x, float %y) {
%1 = fcmp ueq float %x, %y
ret i1 %1
}
define i1 @fcmp_float_ugt(float %x, float %y) {
%1 = fcmp ugt float %x, %y
ret i1 %1
}
define i1 @fcmp_float_uge(float %x, float %y) {
%1 = fcmp uge float %x, %y
ret i1 %1
}
define i1 @fcmp_float_ult(float %x, float %y) {
%1 = fcmp ult float %x, %y
ret i1 %1
}
define i1 @fcmp_float_ule(float %x, float %y) {
%1 = fcmp ule float %x, %y
ret i1 %1
}
define i1 @fcmp_float_une(float %x, float %y) {
%1 = fcmp une float %x, %y
ret i1 %1
}
define i1 @fcmp_double_oeq(double %x, double %y) {
%1 = fcmp oeq double %x, %y
ret i1 %1
}
define i1 @fcmp_double_ogt(double %x, double %y) {
%1 = fcmp ogt double %x, %y
ret i1 %1
}
define i1 @fcmp_double_oge(double %x, double %y) {
%1 = fcmp oge double %x, %y
ret i1 %1
}
define i1 @fcmp_double_olt(double %x, double %y) {
%1 = fcmp olt double %x, %y
ret i1 %1
}
define i1 @fcmp_double_ole(double %x, double %y) {
%1 = fcmp ole double %x, %y
ret i1 %1
}
define i1 @fcmp_double_one(double %x, double %y) {
%1 = fcmp one double %x, %y
ret i1 %1
}
define i1 @fcmp_double_ord(double %x, double %y) {
%1 = fcmp ord double %x, %y
ret i1 %1
}
define i1 @fcmp_double_uno(double %x, double %y) {
%1 = fcmp uno double %x, %y
ret i1 %1
}
define i1 @fcmp_double_ueq(double %x, double %y) {
%1 = fcmp ueq double %x, %y
ret i1 %1
}
define i1 @fcmp_double_ugt(double %x, double %y) {
%1 = fcmp ugt double %x, %y
ret i1 %1
}
define i1 @fcmp_double_uge(double %x, double %y) {
%1 = fcmp uge double %x, %y
ret i1 %1
}
define i1 @fcmp_double_ult(double %x, double %y) {
%1 = fcmp ult double %x, %y
ret i1 %1
}
define i1 @fcmp_double_ule(double %x, double %y) {
%1 = fcmp ule double %x, %y
ret i1 %1
}
define i1 @fcmp_double_une(double %x, double %y) {
%1 = fcmp une double %x, %y
ret i1 %1
}
...
---
name: test_add_i8
alignment: 4
legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $edi, $esi
; FAST-LABEL: name: test_add_i8
; FAST: liveins: $edi, $esi
; FAST: [[COPY:%[0-9]+]]:gpr(s8) = COPY $dil
; FAST: [[COPY1:%[0-9]+]]:gpr(s8) = COPY $sil
; FAST: [[ADD:%[0-9]+]]:gpr(s8) = G_ADD [[COPY]], [[COPY1]]
; FAST: $al = COPY [[ADD]](s8)
; FAST: RET 0, implicit $al
; GREEDY-LABEL: name: test_add_i8
; GREEDY: liveins: $edi, $esi
; GREEDY: [[COPY:%[0-9]+]]:gpr(s8) = COPY $dil
; GREEDY: [[COPY1:%[0-9]+]]:gpr(s8) = COPY $sil
; GREEDY: [[ADD:%[0-9]+]]:gpr(s8) = G_ADD [[COPY]], [[COPY1]]
; GREEDY: $al = COPY [[ADD]](s8)
; GREEDY: RET 0, implicit $al
%0(s8) = COPY $dil
%1(s8) = COPY $sil
%2(s8) = G_ADD %0, %1
$al = COPY %2(s8)
RET 0, implicit $al
...
---
name: test_add_i16
alignment: 4
legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $edi, $esi
; FAST-LABEL: name: test_add_i16
; FAST: liveins: $edi, $esi
; FAST: [[COPY:%[0-9]+]]:gpr(s16) = COPY $di
; FAST: [[COPY1:%[0-9]+]]:gpr(s16) = COPY $si
; FAST: [[ADD:%[0-9]+]]:gpr(s16) = G_ADD [[COPY]], [[COPY1]]
; FAST: $ax = COPY [[ADD]](s16)
; FAST: RET 0, implicit $ax
; GREEDY-LABEL: name: test_add_i16
; GREEDY: liveins: $edi, $esi
; GREEDY: [[COPY:%[0-9]+]]:gpr(s16) = COPY $di
; GREEDY: [[COPY1:%[0-9]+]]:gpr(s16) = COPY $si
; GREEDY: [[ADD:%[0-9]+]]:gpr(s16) = G_ADD [[COPY]], [[COPY1]]
; GREEDY: $ax = COPY [[ADD]](s16)
; GREEDY: RET 0, implicit $ax
%0(s16) = COPY $di
%1(s16) = COPY $si
%2(s16) = G_ADD %0, %1
$ax = COPY %2(s16)
RET 0, implicit $ax
...
---
name: test_add_i32
alignment: 4
legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $edi, $esi
; FAST-LABEL: name: test_add_i32
; FAST: liveins: $edi, $esi
; FAST: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
; FAST: [[COPY1:%[0-9]+]]:gpr(s32) = COPY $esi
; FAST: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[COPY]], [[COPY1]]
; FAST: $eax = COPY [[ADD]](s32)
; FAST: RET 0, implicit $eax
; GREEDY-LABEL: name: test_add_i32
; GREEDY: liveins: $edi, $esi
; GREEDY: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
; GREEDY: [[COPY1:%[0-9]+]]:gpr(s32) = COPY $esi
; GREEDY: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[COPY]], [[COPY1]]
; GREEDY: $eax = COPY [[ADD]](s32)
; GREEDY: RET 0, implicit $eax
%0(s32) = COPY $edi
%1(s32) = COPY $esi
%2(s32) = G_ADD %0, %1
$eax = COPY %2(s32)
RET 0, implicit $eax
...
---
name: test_add_i64
alignment: 4
legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $rdi, $rsi
; FAST-LABEL: name: test_add_i64
; FAST: liveins: $rdi, $rsi
; FAST: [[COPY:%[0-9]+]]:gpr(s64) = COPY $rdi
; FAST: [[COPY1:%[0-9]+]]:gpr(s64) = COPY $rsi
; FAST: [[ADD:%[0-9]+]]:gpr(s64) = G_ADD [[COPY]], [[COPY1]]
; FAST: $rax = COPY [[ADD]](s64)
; FAST: RET 0, implicit $rax
; GREEDY-LABEL: name: test_add_i64
; GREEDY: liveins: $rdi, $rsi
; GREEDY: [[COPY:%[0-9]+]]:gpr(s64) = COPY $rdi
; GREEDY: [[COPY1:%[0-9]+]]:gpr(s64) = COPY $rsi
; GREEDY: [[ADD:%[0-9]+]]:gpr(s64) = G_ADD [[COPY]], [[COPY1]]
; GREEDY: $rax = COPY [[ADD]](s64)
; GREEDY: RET 0, implicit $rax
%0(s64) = COPY $rdi
%1(s64) = COPY $rsi
%2(s64) = G_ADD %0, %1
$rax = COPY %2(s64)
RET 0, implicit $rax
...
---
name: test_mul_gpr
alignment: 4
legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
- { id: 6, class: _ }
- { id: 7, class: _ }
body: |
bb.1 (%ir-block.0):
; FAST-LABEL: name: test_mul_gpr
; FAST: [[DEF:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF
; FAST: [[DEF1:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF
; FAST: [[DEF2:%[0-9]+]]:gpr(s16) = IMPLICIT_DEF
; FAST: [[DEF3:%[0-9]+]]:gpr(s8) = IMPLICIT_DEF
; FAST: [[MUL:%[0-9]+]]:gpr(s64) = G_MUL [[DEF]], [[DEF]]
; FAST: [[MUL1:%[0-9]+]]:gpr(s32) = G_MUL [[DEF1]], [[DEF1]]
; FAST: [[MUL2:%[0-9]+]]:gpr(s16) = G_MUL [[DEF2]], [[DEF2]]
; FAST: [[MUL3:%[0-9]+]]:gpr(s8) = G_MUL [[DEF3]], [[DEF3]]
; FAST: RET 0
; GREEDY-LABEL: name: test_mul_gpr
; GREEDY: [[DEF:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF
; GREEDY: [[DEF1:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF
; GREEDY: [[DEF2:%[0-9]+]]:gpr(s16) = IMPLICIT_DEF
; GREEDY: [[DEF3:%[0-9]+]]:gpr(s8) = IMPLICIT_DEF
; GREEDY: [[MUL:%[0-9]+]]:gpr(s64) = G_MUL [[DEF]], [[DEF]]
; GREEDY: [[MUL1:%[0-9]+]]:gpr(s32) = G_MUL [[DEF1]], [[DEF1]]
; GREEDY: [[MUL2:%[0-9]+]]:gpr(s16) = G_MUL [[DEF2]], [[DEF2]]
; GREEDY: [[MUL3:%[0-9]+]]:gpr(s8) = G_MUL [[DEF3]], [[DEF3]]
; GREEDY: RET 0
%0(s64) = IMPLICIT_DEF
%1(s32) = IMPLICIT_DEF
%2(s16) = IMPLICIT_DEF
%3(s8) = IMPLICIT_DEF
%4(s64) = G_MUL %0, %0
%5(s32) = G_MUL %1, %1
%6(s16) = G_MUL %2, %2
%7(s8) = G_MUL %3, %3
RET 0
...
---
name: test_add_float
alignment: 4
legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $xmm0, $xmm1
; FAST-LABEL: name: test_add_float
; FAST: liveins: $xmm0, $xmm1
; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
; FAST: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128)
; FAST: [[COPY1:%[0-9]+]]:vecr(s128) = COPY $xmm1
; FAST: [[TRUNC1:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY1]](s128)
; FAST: [[FADD:%[0-9]+]]:vecr(s32) = G_FADD [[TRUNC]], [[TRUNC1]]
; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FADD]](s32)
; FAST: $xmm0 = COPY [[ANYEXT]](s128)
; FAST: RET 0, implicit $xmm0
; GREEDY-LABEL: name: test_add_float
; GREEDY: liveins: $xmm0, $xmm1
; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128)
; GREEDY: [[COPY1:%[0-9]+]]:vecr(s128) = COPY $xmm1
; GREEDY: [[TRUNC1:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY1]](s128)
; GREEDY: [[FADD:%[0-9]+]]:vecr(s32) = G_FADD [[TRUNC]], [[TRUNC1]]
; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FADD]](s32)
; GREEDY: $xmm0 = COPY [[ANYEXT]](s128)
; GREEDY: RET 0, implicit $xmm0
%2:_(s128) = COPY $xmm0
%0:_(s32) = G_TRUNC %2(s128)
%3:_(s128) = COPY $xmm1
%1:_(s32) = G_TRUNC %3(s128)
%4:_(s32) = G_FADD %0, %1
%5:_(s128) = G_ANYEXT %4(s32)
$xmm0 = COPY %5(s128)
RET 0, implicit $xmm0
...
---
name: test_add_double
alignment: 4
legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $xmm0, $xmm1
; FAST-LABEL: name: test_add_double
; FAST: liveins: $xmm0, $xmm1
; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
; FAST: [[TRUNC:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY]](s128)
; FAST: [[COPY1:%[0-9]+]]:vecr(s128) = COPY $xmm1
; FAST: [[TRUNC1:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY1]](s128)
; FAST: [[FADD:%[0-9]+]]:vecr(s64) = G_FADD [[TRUNC]], [[TRUNC1]]
; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FADD]](s64)
; FAST: $xmm0 = COPY [[ANYEXT]](s128)
; FAST: RET 0, implicit $xmm0
; GREEDY-LABEL: name: test_add_double
; GREEDY: liveins: $xmm0, $xmm1
; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY]](s128)
; GREEDY: [[COPY1:%[0-9]+]]:vecr(s128) = COPY $xmm1
; GREEDY: [[TRUNC1:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY1]](s128)
; GREEDY: [[FADD:%[0-9]+]]:vecr(s64) = G_FADD [[TRUNC]], [[TRUNC1]]
; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FADD]](s64)
; GREEDY: $xmm0 = COPY [[ANYEXT]](s128)
; GREEDY: RET 0, implicit $xmm0
%2:_(s128) = COPY $xmm0
%0:_(s64) = G_TRUNC %2(s128)
%3:_(s128) = COPY $xmm1
%1:_(s64) = G_TRUNC %3(s128)
%4:_(s64) = G_FADD %0, %1
%5:_(s128) = G_ANYEXT %4(s64)
$xmm0 = COPY %5(s128)
RET 0, implicit $xmm0
...
---
name: test_fsub_float
alignment: 4
legalized: true
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
- { id: 2, class: _, preferred-register: '' }
- { id: 3, class: _, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
body: |
bb.1 (%ir-block.0):
; FAST-LABEL: name: test_fsub_float
; FAST: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF
; FAST: [[DEF1:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF
; FAST: [[COPY:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32)
; FAST: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32)
; FAST: [[FSUB:%[0-9]+]]:vecr(s32) = G_FSUB [[COPY]], [[COPY1]]
; FAST: [[COPY2:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64)
; FAST: [[COPY3:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64)
; FAST: [[FSUB1:%[0-9]+]]:vecr(s64) = G_FSUB [[COPY2]], [[COPY3]]
; FAST: RET 0
; GREEDY-LABEL: name: test_fsub_float
; GREEDY: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF
; GREEDY: [[DEF1:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF
; GREEDY: [[COPY:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32)
; GREEDY: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32)
; GREEDY: [[FSUB:%[0-9]+]]:vecr(s32) = G_FSUB [[COPY]], [[COPY1]]
; GREEDY: [[COPY2:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64)
; GREEDY: [[COPY3:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64)
; GREEDY: [[FSUB1:%[0-9]+]]:vecr(s64) = G_FSUB [[COPY2]], [[COPY3]]
; GREEDY: RET 0
%0(s32) = IMPLICIT_DEF
%2(s64) = IMPLICIT_DEF
%1(s32) = G_FSUB %0, %0
%3(s64) = G_FSUB %2, %2
RET 0
...
---
name: test_fmul_float
alignment: 4
legalized: true
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
- { id: 2, class: _, preferred-register: '' }
- { id: 3, class: _, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
body: |
bb.1 (%ir-block.0):
; FAST-LABEL: name: test_fmul_float
; FAST: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF
; FAST: [[DEF1:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF
; FAST: [[COPY:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32)
; FAST: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32)
; FAST: [[FMUL:%[0-9]+]]:vecr(s32) = G_FMUL [[COPY]], [[COPY1]]
; FAST: [[COPY2:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64)
; FAST: [[COPY3:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64)
; FAST: [[FMUL1:%[0-9]+]]:vecr(s64) = G_FMUL [[COPY2]], [[COPY3]]
; FAST: RET 0
; GREEDY-LABEL: name: test_fmul_float
; GREEDY: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF
; GREEDY: [[DEF1:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF
; GREEDY: [[COPY:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32)
; GREEDY: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32)
; GREEDY: [[FMUL:%[0-9]+]]:vecr(s32) = G_FMUL [[COPY]], [[COPY1]]
; GREEDY: [[COPY2:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64)
; GREEDY: [[COPY3:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64)
; GREEDY: [[FMUL1:%[0-9]+]]:vecr(s64) = G_FMUL [[COPY2]], [[COPY3]]
; GREEDY: RET 0
%0(s32) = IMPLICIT_DEF
%2(s64) = IMPLICIT_DEF
%1(s32) = G_FMUL %0, %0
%3(s64) = G_FMUL %2, %2
RET 0
...
---
name: test_fdiv_float
alignment: 4
legalized: true
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
- { id: 2, class: _, preferred-register: '' }
- { id: 3, class: _, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
body: |
bb.1 (%ir-block.0):
; FAST-LABEL: name: test_fdiv_float
; FAST: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF
; FAST: [[DEF1:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF
; FAST: [[COPY:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32)
; FAST: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32)
; FAST: [[FDIV:%[0-9]+]]:vecr(s32) = G_FDIV [[COPY]], [[COPY1]]
; FAST: [[COPY2:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64)
; FAST: [[COPY3:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64)
; FAST: [[FDIV1:%[0-9]+]]:vecr(s64) = G_FDIV [[COPY2]], [[COPY3]]
; FAST: RET 0
; GREEDY-LABEL: name: test_fdiv_float
; GREEDY: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF
; GREEDY: [[DEF1:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF
; GREEDY: [[COPY:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32)
; GREEDY: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32)
; GREEDY: [[FDIV:%[0-9]+]]:vecr(s32) = G_FDIV [[COPY]], [[COPY1]]
; GREEDY: [[COPY2:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64)
; GREEDY: [[COPY3:%[0-9]+]]:vecr(s64) = COPY [[DEF1]](s64)
; GREEDY: [[FDIV1:%[0-9]+]]:vecr(s64) = G_FDIV [[COPY2]], [[COPY3]]
; GREEDY: RET 0
%0(s32) = IMPLICIT_DEF
%2(s64) = IMPLICIT_DEF
%1(s32) = G_FDIV %0, %0
%3(s64) = G_FDIV %2, %2
RET 0
...
---
name: test_add_v4i32
alignment: 4
legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $xmm0, $xmm1
; FAST-LABEL: name: test_add_v4i32
; FAST: liveins: $xmm0, $xmm1
; FAST: [[COPY:%[0-9]+]]:vecr(<4 x s32>) = COPY $xmm0
; FAST: [[COPY1:%[0-9]+]]:vecr(<4 x s32>) = COPY $xmm1
; FAST: [[ADD:%[0-9]+]]:vecr(<4 x s32>) = G_ADD [[COPY]], [[COPY1]]
; FAST: $xmm0 = COPY [[ADD]](<4 x s32>)
; FAST: RET 0, implicit $xmm0
; GREEDY-LABEL: name: test_add_v4i32
; GREEDY: liveins: $xmm0, $xmm1
; GREEDY: [[COPY:%[0-9]+]]:vecr(<4 x s32>) = COPY $xmm0
; GREEDY: [[COPY1:%[0-9]+]]:vecr(<4 x s32>) = COPY $xmm1
; GREEDY: [[ADD:%[0-9]+]]:vecr(<4 x s32>) = G_ADD [[COPY]], [[COPY1]]
; GREEDY: $xmm0 = COPY [[ADD]](<4 x s32>)
; GREEDY: RET 0, implicit $xmm0
%0(<4 x s32>) = COPY $xmm0
%1(<4 x s32>) = COPY $xmm1
%2(<4 x s32>) = G_ADD %0, %1
$xmm0 = COPY %2(<4 x s32>)
RET 0, implicit $xmm0
...
---
name: test_add_v4f32
alignment: 4
legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $xmm0, $xmm1
; FAST-LABEL: name: test_add_v4f32
; FAST: liveins: $xmm0, $xmm1
; FAST: [[COPY:%[0-9]+]]:vecr(<4 x s32>) = COPY $xmm0
; FAST: [[COPY1:%[0-9]+]]:vecr(<4 x s32>) = COPY $xmm1
; FAST: [[FADD:%[0-9]+]]:vecr(<4 x s32>) = G_FADD [[COPY]], [[COPY1]]
; FAST: $xmm0 = COPY [[FADD]](<4 x s32>)
; FAST: RET 0, implicit $xmm0
; GREEDY-LABEL: name: test_add_v4f32
; GREEDY: liveins: $xmm0, $xmm1
; GREEDY: [[COPY:%[0-9]+]]:vecr(<4 x s32>) = COPY $xmm0
; GREEDY: [[COPY1:%[0-9]+]]:vecr(<4 x s32>) = COPY $xmm1
; GREEDY: [[FADD:%[0-9]+]]:vecr(<4 x s32>) = G_FADD [[COPY]], [[COPY1]]
; GREEDY: $xmm0 = COPY [[FADD]](<4 x s32>)
; GREEDY: RET 0, implicit $xmm0
%0(<4 x s32>) = COPY $xmm0
%1(<4 x s32>) = COPY $xmm1
%2(<4 x s32>) = G_FADD %0, %1
$xmm0 = COPY %2(<4 x s32>)
RET 0, implicit $xmm0
...
---
name: test_load_i8
alignment: 4
legalized: true
regBankSelected: false
selected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $rdi
; FAST-LABEL: name: test_load_i8
; FAST: [[COPY:%[0-9]+]]:gpr(p0) = COPY $rdi
; FAST: [[LOAD:%[0-9]+]]:gpr(s8) = G_LOAD [[COPY]](p0) :: (load 1 from %ir.p1)
; FAST: $al = COPY [[LOAD]](s8)
; FAST: RET 0, implicit $al
; GREEDY-LABEL: name: test_load_i8
; GREEDY: [[COPY:%[0-9]+]]:gpr(p0) = COPY $rdi
; GREEDY: [[LOAD:%[0-9]+]]:gpr(s8) = G_LOAD [[COPY]](p0) :: (load 1 from %ir.p1)
; GREEDY: $al = COPY [[LOAD]](s8)
; GREEDY: RET 0, implicit $al
%0(p0) = COPY $rdi
%1(s8) = G_LOAD %0(p0) :: (load 1 from %ir.p1)
$al = COPY %1(s8)
RET 0, implicit $al
...
---
name: test_load_i16
alignment: 4
legalized: true
regBankSelected: false
selected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $rdi
; FAST-LABEL: name: test_load_i16
; FAST: [[COPY:%[0-9]+]]:gpr(p0) = COPY $rdi
; FAST: [[LOAD:%[0-9]+]]:gpr(s16) = G_LOAD [[COPY]](p0) :: (load 2 from %ir.p1)
; FAST: $ax = COPY [[LOAD]](s16)
; FAST: RET 0, implicit $ax
; GREEDY-LABEL: name: test_load_i16
; GREEDY: [[COPY:%[0-9]+]]:gpr(p0) = COPY $rdi
; GREEDY: [[LOAD:%[0-9]+]]:gpr(s16) = G_LOAD [[COPY]](p0) :: (load 2 from %ir.p1)
; GREEDY: $ax = COPY [[LOAD]](s16)
; GREEDY: RET 0, implicit $ax
%0(p0) = COPY $rdi
%1(s16) = G_LOAD %0(p0) :: (load 2 from %ir.p1)
$ax = COPY %1(s16)
RET 0, implicit $ax
...
---
name: test_load_i32
alignment: 4
legalized: true
regBankSelected: false
selected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $rdi
; FAST-LABEL: name: test_load_i32
; FAST: [[COPY:%[0-9]+]]:gpr(p0) = COPY $rdi
; FAST: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.p1)
; FAST: $eax = COPY [[LOAD]](s32)
; FAST: RET 0, implicit $eax
; GREEDY-LABEL: name: test_load_i32
; GREEDY: [[COPY:%[0-9]+]]:gpr(p0) = COPY $rdi
; GREEDY: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.p1)
; GREEDY: $eax = COPY [[LOAD]](s32)
; GREEDY: RET 0, implicit $eax
%0(p0) = COPY $rdi
%1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
$eax = COPY %1(s32)
RET 0, implicit $eax
...
---
name: test_load_i64
alignment: 4
exposesReturnsTwice: false
legalized: true
regBankSelected: false
selected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $rdi
; FAST-LABEL: name: test_load_i64
; FAST: [[COPY:%[0-9]+]]:gpr(p0) = COPY $rdi
; FAST: [[LOAD:%[0-9]+]]:gpr(s64) = G_LOAD [[COPY]](p0) :: (load 8 from %ir.p1)
; FAST: $rax = COPY [[LOAD]](s64)
; FAST: RET 0, implicit $rax
; GREEDY-LABEL: name: test_load_i64
; GREEDY: [[COPY:%[0-9]+]]:gpr(p0) = COPY $rdi
; GREEDY: [[LOAD:%[0-9]+]]:gpr(s64) = G_LOAD [[COPY]](p0) :: (load 8 from %ir.p1)
; GREEDY: $rax = COPY [[LOAD]](s64)
; GREEDY: RET 0, implicit $rax
%0(p0) = COPY $rdi
%1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1)
$rax = COPY %1(s64)
RET 0, implicit $rax
...
---
name: test_load_float
alignment: 4
legalized: true
regBankSelected: false
selected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $rdi
; FAST-LABEL: name: test_load_float
; FAST: [[COPY:%[0-9]+]]:gpr(p0) = COPY $rdi
; FAST: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.p1)
; FAST: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[LOAD]](s32)
; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[COPY1]](s32)
; FAST: $xmm0 = COPY [[ANYEXT]](s128)
; FAST: RET 0, implicit $xmm0
; GREEDY-LABEL: name: test_load_float
; GREEDY: [[COPY:%[0-9]+]]:gpr(p0) = COPY $rdi
; GREEDY: [[LOAD:%[0-9]+]]:gpr(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.p1)
; GREEDY: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[LOAD]](s32)
; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[COPY1]](s32)
; GREEDY: $xmm0 = COPY [[ANYEXT]](s128)
; GREEDY: RET 0, implicit $xmm0
%0:_(p0) = COPY $rdi
%1:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
%2:_(s128) = G_ANYEXT %1(s32)
$xmm0 = COPY %2(s128)
RET 0, implicit $xmm0
...
---
name: test_load_double
alignment: 4
legalized: true
regBankSelected: false
selected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $rdi
; FAST-LABEL: name: test_load_double
; FAST: [[COPY:%[0-9]+]]:gpr(p0) = COPY $rdi
; FAST: [[LOAD:%[0-9]+]]:gpr(s64) = G_LOAD [[COPY]](p0) :: (load 8 from %ir.p1)
; FAST: [[COPY1:%[0-9]+]]:vecr(s64) = COPY [[LOAD]](s64)
; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[COPY1]](s64)
; FAST: $xmm0 = COPY [[ANYEXT]](s128)
; FAST: RET 0, implicit $xmm0
; GREEDY-LABEL: name: test_load_double
; GREEDY: [[COPY:%[0-9]+]]:gpr(p0) = COPY $rdi
; GREEDY: [[LOAD:%[0-9]+]]:gpr(s64) = G_LOAD [[COPY]](p0) :: (load 8 from %ir.p1)
; GREEDY: [[COPY1:%[0-9]+]]:vecr(s64) = COPY [[LOAD]](s64)
; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[COPY1]](s64)
; GREEDY: $xmm0 = COPY [[ANYEXT]](s128)
; GREEDY: RET 0, implicit $xmm0
%0:_(p0) = COPY $rdi
%1:_(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1)
%2:_(s128) = G_ANYEXT %1(s64)
$xmm0 = COPY %2(s128)
RET 0, implicit $xmm0
...
---
name: test_load_v4i32
alignment: 4
legalized: true
regBankSelected: false
selected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $rdi
; FAST-LABEL: name: test_load_v4i32
; FAST: [[COPY:%[0-9]+]]:gpr(p0) = COPY $rdi
; FAST: [[LOAD:%[0-9]+]]:vecr(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.p1, align 1)
; FAST: $xmm0 = COPY [[LOAD]](<4 x s32>)
; FAST: RET 0, implicit $xmm0
; GREEDY-LABEL: name: test_load_v4i32
; GREEDY: [[COPY:%[0-9]+]]:gpr(p0) = COPY $rdi
; GREEDY: [[LOAD:%[0-9]+]]:vecr(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.p1, align 1)
; GREEDY: $xmm0 = COPY [[LOAD]](<4 x s32>)
; GREEDY: RET 0, implicit $xmm0
%0(p0) = COPY $rdi
%1(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.p1, align 1)
$xmm0 = COPY %1(<4 x s32>)
RET 0, implicit $xmm0
...
---
name: test_store_i32
alignment: 4
legalized: true
regBankSelected: false
selected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $edi, $rsi
; FAST-LABEL: name: test_store_i32
; FAST: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
; FAST: [[COPY1:%[0-9]+]]:gpr(p0) = COPY $rsi
; FAST: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store 4 into %ir.p1)
; FAST: $rax = COPY [[COPY1]](p0)
; FAST: RET 0, implicit $rax
; GREEDY-LABEL: name: test_store_i32
; GREEDY: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
; GREEDY: [[COPY1:%[0-9]+]]:gpr(p0) = COPY $rsi
; GREEDY: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store 4 into %ir.p1)
; GREEDY: $rax = COPY [[COPY1]](p0)
; GREEDY: RET 0, implicit $rax
%0(s32) = COPY $edi
%1(p0) = COPY $rsi
G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1)
$rax = COPY %1(p0)
RET 0, implicit $rax
...
---
name: test_store_i64
alignment: 4
legalized: true
regBankSelected: false
selected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $rdi, $rsi
; FAST-LABEL: name: test_store_i64
; FAST: [[COPY:%[0-9]+]]:gpr(s64) = COPY $rdi
; FAST: [[COPY1:%[0-9]+]]:gpr(p0) = COPY $rsi
; FAST: G_STORE [[COPY]](s64), [[COPY1]](p0) :: (store 8 into %ir.p1)
; FAST: $rax = COPY [[COPY1]](p0)
; FAST: RET 0, implicit $rax
; GREEDY-LABEL: name: test_store_i64
; GREEDY: [[COPY:%[0-9]+]]:gpr(s64) = COPY $rdi
; GREEDY: [[COPY1:%[0-9]+]]:gpr(p0) = COPY $rsi
; GREEDY: G_STORE [[COPY]](s64), [[COPY1]](p0) :: (store 8 into %ir.p1)
; GREEDY: $rax = COPY [[COPY1]](p0)
; GREEDY: RET 0, implicit $rax
%0(s64) = COPY $rdi
%1(p0) = COPY $rsi
G_STORE %0(s64), %1(p0) :: (store 8 into %ir.p1)
$rax = COPY %1(p0)
RET 0, implicit $rax
...
---
name: test_store_float
alignment: 4
legalized: true
regBankSelected: false
selected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $rdi, $xmm0
; FAST-LABEL: name: test_store_float
; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
; FAST: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128)
; FAST: [[COPY1:%[0-9]+]]:gpr(p0) = COPY $rdi
; FAST: [[COPY2:%[0-9]+]]:gpr(s32) = COPY [[TRUNC]](s32)
; FAST: G_STORE [[COPY2]](s32), [[COPY1]](p0) :: (store 4 into %ir.p1)
; FAST: $rax = COPY [[COPY1]](p0)
; FAST: RET 0, implicit $rax
; GREEDY-LABEL: name: test_store_float
; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128)
; GREEDY: [[COPY1:%[0-9]+]]:gpr(p0) = COPY $rdi
; GREEDY: G_STORE [[TRUNC]](s32), [[COPY1]](p0) :: (store 4 into %ir.p1)
; GREEDY: $rax = COPY [[COPY1]](p0)
; GREEDY: RET 0, implicit $rax
%2:_(s128) = COPY $xmm0
%0:_(s32) = G_TRUNC %2(s128)
%1:_(p0) = COPY $rdi
G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1)
$rax = COPY %1(p0)
RET 0, implicit $rax
...
---
name: test_store_double
alignment: 4
legalized: true
regBankSelected: false
selected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $rdi, $xmm0
; FAST-LABEL: name: test_store_double
; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
; FAST: [[TRUNC:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY]](s128)
; FAST: [[COPY1:%[0-9]+]]:gpr(p0) = COPY $rdi
; FAST: [[COPY2:%[0-9]+]]:gpr(s64) = COPY [[TRUNC]](s64)
; FAST: G_STORE [[COPY2]](s64), [[COPY1]](p0) :: (store 8 into %ir.p1)
; FAST: $rax = COPY [[COPY1]](p0)
; FAST: RET 0, implicit $rax
; GREEDY-LABEL: name: test_store_double
; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY]](s128)
; GREEDY: [[COPY1:%[0-9]+]]:gpr(p0) = COPY $rdi
; GREEDY: G_STORE [[TRUNC]](s64), [[COPY1]](p0) :: (store 8 into %ir.p1)
; GREEDY: $rax = COPY [[COPY1]](p0)
; GREEDY: RET 0, implicit $rax
%2:_(s128) = COPY $xmm0
%0:_(s64) = G_TRUNC %2(s128)
%1:_(p0) = COPY $rdi
G_STORE %0(s64), %1(p0) :: (store 8 into %ir.p1)
$rax = COPY %1(p0)
RET 0, implicit $rax
...
---
name: constInt_check
alignment: 4
legalized: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
body: |
bb.0 (%ir-block.0):
; FAST-LABEL: name: constInt_check
; FAST: [[C:%[0-9]+]]:gpr(s8) = G_CONSTANT i8 8
; FAST: [[C1:%[0-9]+]]:gpr(s16) = G_CONSTANT i16 16
; FAST: [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 32
; FAST: [[C3:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 64
; FAST: RET 0
; GREEDY-LABEL: name: constInt_check
; GREEDY: [[C:%[0-9]+]]:gpr(s8) = G_CONSTANT i8 8
; GREEDY: [[C1:%[0-9]+]]:gpr(s16) = G_CONSTANT i16 16
; GREEDY: [[C2:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 32
; GREEDY: [[C3:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 64
; GREEDY: RET 0
%0(s8) = G_CONSTANT i8 8
%1(s16) = G_CONSTANT i16 16
%2(s32) = G_CONSTANT i32 32
%3(s64) = G_CONSTANT i64 64
RET 0
...
---
name: trunc_check
alignment: 4
legalized: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
body: |
bb.0 (%ir-block.0):
; FAST-LABEL: name: trunc_check
; FAST: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF
; FAST: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[DEF]](s32)
; FAST: [[TRUNC1:%[0-9]+]]:gpr(s8) = G_TRUNC [[DEF]](s32)
; FAST: [[TRUNC2:%[0-9]+]]:gpr(s16) = G_TRUNC [[DEF]](s32)
; FAST: RET 0
; GREEDY-LABEL: name: trunc_check
; GREEDY: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF
; GREEDY: [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[DEF]](s32)
; GREEDY: [[TRUNC1:%[0-9]+]]:gpr(s8) = G_TRUNC [[DEF]](s32)
; GREEDY: [[TRUNC2:%[0-9]+]]:gpr(s16) = G_TRUNC [[DEF]](s32)
; GREEDY: RET 0
%0(s32) = IMPLICIT_DEF
%1(s1) = G_TRUNC %0(s32)
%2(s8) = G_TRUNC %0(s32)
%3(s16) = G_TRUNC %0(s32)
RET 0
...
---
name: test_gep
legalized: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
body: |
bb.0 (%ir-block.0):
; FAST-LABEL: name: test_gep
; FAST: [[DEF:%[0-9]+]]:gpr(p0) = IMPLICIT_DEF
; FAST: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 20
; FAST: [[GEP:%[0-9]+]]:gpr(p0) = G_GEP [[DEF]], [[C]](s32)
; FAST: [[C1:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 20
; FAST: [[GEP1:%[0-9]+]]:gpr(p0) = G_GEP [[DEF]], [[C1]](s64)
; FAST: RET 0
; GREEDY-LABEL: name: test_gep
; GREEDY: [[DEF:%[0-9]+]]:gpr(p0) = IMPLICIT_DEF
; GREEDY: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 20
; GREEDY: [[GEP:%[0-9]+]]:gpr(p0) = G_GEP [[DEF]], [[C]](s32)
; GREEDY: [[C1:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 20
; GREEDY: [[GEP1:%[0-9]+]]:gpr(p0) = G_GEP [[DEF]], [[C1]](s64)
; GREEDY: RET 0
%0(p0) = IMPLICIT_DEF
%1(s32) = G_CONSTANT i32 20
%2(p0) = G_GEP %0, %1(s32)
%3(s64) = G_CONSTANT i64 20
%4(p0) = G_GEP %0, %3(s64)
RET 0
...
---
name: test_icmp_eq_i8
alignment: 4
legalized: true
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $edi, $esi
; FAST-LABEL: name: test_icmp_eq_i8
; FAST: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
; FAST: [[TRUNC:%[0-9]+]]:gpr(s8) = G_TRUNC [[COPY]](s32)
; FAST: [[COPY1:%[0-9]+]]:gpr(s32) = COPY $esi
; FAST: [[TRUNC1:%[0-9]+]]:gpr(s8) = G_TRUNC [[COPY1]](s32)
; FAST: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(eq), [[TRUNC]](s8), [[TRUNC1]]
; FAST: [[ANYEXT:%[0-9]+]]:gpr(s8) = G_ANYEXT [[ICMP]](s1)
; FAST: $al = COPY [[ANYEXT]](s8)
; FAST: RET 0, implicit $al
; GREEDY-LABEL: name: test_icmp_eq_i8
; GREEDY: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
; GREEDY: [[TRUNC:%[0-9]+]]:gpr(s8) = G_TRUNC [[COPY]](s32)
; GREEDY: [[COPY1:%[0-9]+]]:gpr(s32) = COPY $esi
; GREEDY: [[TRUNC1:%[0-9]+]]:gpr(s8) = G_TRUNC [[COPY1]](s32)
; GREEDY: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(eq), [[TRUNC]](s8), [[TRUNC1]]
; GREEDY: [[ANYEXT:%[0-9]+]]:gpr(s8) = G_ANYEXT [[ICMP]](s1)
; GREEDY: $al = COPY [[ANYEXT]](s8)
; GREEDY: RET 0, implicit $al
%2:_(s32) = COPY $edi
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $esi
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s1) = G_ICMP intpred(eq), %0(s8), %1
%5:_(s8) = G_ANYEXT %4(s1)
$al = COPY %5(s8)
RET 0, implicit $al
...
---
name: test_icmp_eq_i16
alignment: 4
legalized: true
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $edi, $esi
; FAST-LABEL: name: test_icmp_eq_i16
; FAST: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
; FAST: [[TRUNC:%[0-9]+]]:gpr(s16) = G_TRUNC [[COPY]](s32)
; FAST: [[COPY1:%[0-9]+]]:gpr(s32) = COPY $esi
; FAST: [[TRUNC1:%[0-9]+]]:gpr(s16) = G_TRUNC [[COPY1]](s32)
; FAST: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(eq), [[TRUNC]](s16), [[TRUNC1]]
; FAST: [[ANYEXT:%[0-9]+]]:gpr(s8) = G_ANYEXT [[ICMP]](s1)
; FAST: $al = COPY [[ANYEXT]](s8)
; FAST: RET 0, implicit $al
; GREEDY-LABEL: name: test_icmp_eq_i16
; GREEDY: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
; GREEDY: [[TRUNC:%[0-9]+]]:gpr(s16) = G_TRUNC [[COPY]](s32)
; GREEDY: [[COPY1:%[0-9]+]]:gpr(s32) = COPY $esi
; GREEDY: [[TRUNC1:%[0-9]+]]:gpr(s16) = G_TRUNC [[COPY1]](s32)
; GREEDY: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(eq), [[TRUNC]](s16), [[TRUNC1]]
; GREEDY: [[ANYEXT:%[0-9]+]]:gpr(s8) = G_ANYEXT [[ICMP]](s1)
; GREEDY: $al = COPY [[ANYEXT]](s8)
; GREEDY: RET 0, implicit $al
%2:_(s32) = COPY $edi
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $esi
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s1) = G_ICMP intpred(eq), %0(s16), %1
%5:_(s8) = G_ANYEXT %4(s1)
$al = COPY %5(s8)
RET 0, implicit $al
...
---
name: test_icmp_eq_i32
alignment: 4
legalized: true
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $edi, $esi
; FAST-LABEL: name: test_icmp_eq_i32
; FAST: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
; FAST: [[COPY1:%[0-9]+]]:gpr(s32) = COPY $esi
; FAST: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
; FAST: [[ANYEXT:%[0-9]+]]:gpr(s8) = G_ANYEXT [[ICMP]](s1)
; FAST: $al = COPY [[ANYEXT]](s8)
; FAST: RET 0, implicit $al
; GREEDY-LABEL: name: test_icmp_eq_i32
; GREEDY: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
; GREEDY: [[COPY1:%[0-9]+]]:gpr(s32) = COPY $esi
; GREEDY: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
; GREEDY: [[ANYEXT:%[0-9]+]]:gpr(s8) = G_ANYEXT [[ICMP]](s1)
; GREEDY: $al = COPY [[ANYEXT]](s8)
; GREEDY: RET 0, implicit $al
%0:_(s32) = COPY $edi
%1:_(s32) = COPY $esi
%2:_(s1) = G_ICMP intpred(eq), %0(s32), %1
%3:_(s8) = G_ANYEXT %2(s1)
$al = COPY %3(s8)
RET 0, implicit $al
...
---
name: test_icmp_eq_i64
alignment: 4
legalized: true
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $rdi, $rsi
; FAST-LABEL: name: test_icmp_eq_i64
; FAST: [[COPY:%[0-9]+]]:gpr(s64) = COPY $rdi
; FAST: [[COPY1:%[0-9]+]]:gpr(s64) = COPY $rsi
; FAST: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(eq), [[COPY]](s64), [[COPY1]]
; FAST: [[ANYEXT:%[0-9]+]]:gpr(s8) = G_ANYEXT [[ICMP]](s1)
; FAST: $al = COPY [[ANYEXT]](s8)
; FAST: RET 0, implicit $al
; GREEDY-LABEL: name: test_icmp_eq_i64
; GREEDY: [[COPY:%[0-9]+]]:gpr(s64) = COPY $rdi
; GREEDY: [[COPY1:%[0-9]+]]:gpr(s64) = COPY $rsi
; GREEDY: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(eq), [[COPY]](s64), [[COPY1]]
; GREEDY: [[ANYEXT:%[0-9]+]]:gpr(s8) = G_ANYEXT [[ICMP]](s1)
; GREEDY: $al = COPY [[ANYEXT]](s8)
; GREEDY: RET 0, implicit $al
%0:_(s64) = COPY $rdi
%1:_(s64) = COPY $rsi
%2:_(s1) = G_ICMP intpred(eq), %0(s64), %1
%3:_(s8) = G_ANYEXT %2(s1)
$al = COPY %3(s8)
RET 0, implicit $al
...
---
name: test_xor_i8
alignment: 4
legalized: true
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
body: |
bb.1 (%ir-block.0):
; FAST-LABEL: name: test_xor_i8
; FAST: [[DEF:%[0-9]+]]:gpr(s8) = IMPLICIT_DEF
; FAST: [[XOR:%[0-9]+]]:gpr(s8) = G_XOR [[DEF]], [[DEF]]
; FAST: $al = COPY [[XOR]](s8)
; FAST: RET 0, implicit $al
; GREEDY-LABEL: name: test_xor_i8
; GREEDY: [[DEF:%[0-9]+]]:gpr(s8) = IMPLICIT_DEF
; GREEDY: [[XOR:%[0-9]+]]:gpr(s8) = G_XOR [[DEF]], [[DEF]]
; GREEDY: $al = COPY [[XOR]](s8)
; GREEDY: RET 0, implicit $al
%0(s8) = IMPLICIT_DEF
%1(s8) = G_XOR %0, %0
$al = COPY %1(s8)
RET 0, implicit $al
...
---
name: test_or_i16
alignment: 4
legalized: true
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
body: |
bb.1 (%ir-block.0):
; FAST-LABEL: name: test_or_i16
; FAST: [[DEF:%[0-9]+]]:gpr(s16) = IMPLICIT_DEF
; FAST: [[OR:%[0-9]+]]:gpr(s16) = G_OR [[DEF]], [[DEF]]
; FAST: $ax = COPY [[OR]](s16)
; FAST: RET 0, implicit $ax
; GREEDY-LABEL: name: test_or_i16
; GREEDY: [[DEF:%[0-9]+]]:gpr(s16) = IMPLICIT_DEF
; GREEDY: [[OR:%[0-9]+]]:gpr(s16) = G_OR [[DEF]], [[DEF]]
; GREEDY: $ax = COPY [[OR]](s16)
; GREEDY: RET 0, implicit $ax
%0(s16) = IMPLICIT_DEF
%1(s16) = G_OR %0, %0
$ax = COPY %1(s16)
RET 0, implicit $ax
...
---
name: test_and_i32
alignment: 4
legalized: true
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
body: |
bb.1 (%ir-block.0):
; FAST-LABEL: name: test_and_i32
; FAST: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF
; FAST: [[AND:%[0-9]+]]:gpr(s32) = G_AND [[DEF]], [[DEF]]
; FAST: $eax = COPY [[AND]](s32)
; FAST: RET 0, implicit $eax
; GREEDY-LABEL: name: test_and_i32
; GREEDY: [[DEF:%[0-9]+]]:gpr(s32) = IMPLICIT_DEF
; GREEDY: [[AND:%[0-9]+]]:gpr(s32) = G_AND [[DEF]], [[DEF]]
; GREEDY: $eax = COPY [[AND]](s32)
; GREEDY: RET 0, implicit $eax
%0(s32) = IMPLICIT_DEF
%1(s32) = G_AND %0, %0
$eax = COPY %1(s32)
RET 0, implicit $eax
...
---
name: test_and_i64
alignment: 4
legalized: true
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
body: |
bb.1 (%ir-block.0):
; FAST-LABEL: name: test_and_i64
; FAST: [[DEF:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF
; FAST: [[AND:%[0-9]+]]:gpr(s64) = G_AND [[DEF]], [[DEF]]
; FAST: $rax = COPY [[AND]](s64)
; FAST: RET 0, implicit $rax
; GREEDY-LABEL: name: test_and_i64
; GREEDY: [[DEF:%[0-9]+]]:gpr(s64) = IMPLICIT_DEF
; GREEDY: [[AND:%[0-9]+]]:gpr(s64) = G_AND [[DEF]], [[DEF]]
; GREEDY: $rax = COPY [[AND]](s64)
; GREEDY: RET 0, implicit $rax
%0(s64) = IMPLICIT_DEF
%1(s64) = G_AND %0, %0
$rax = COPY %1(s64)
RET 0, implicit $rax
...
---
name: test_global_ptrv
alignment: 4
legalized: true
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
body: |
bb.1.entry:
; FAST-LABEL: name: test_global_ptrv
; FAST: [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @g_int
; FAST: $rax = COPY [[GV]](p0)
; FAST: RET 0, implicit $rax
; GREEDY-LABEL: name: test_global_ptrv
; GREEDY: [[GV:%[0-9]+]]:gpr(p0) = G_GLOBAL_VALUE @g_int
; GREEDY: $rax = COPY [[GV]](p0)
; GREEDY: RET 0, implicit $rax
%0(p0) = G_GLOBAL_VALUE @g_int
$rax = COPY %0(p0)
RET 0, implicit $rax
...
---
name: test_undef
alignment: 4
legalized: true
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
body: |
bb.1 (%ir-block.0):
; FAST-LABEL: name: test_undef
; FAST: [[DEF:%[0-9]+]]:gpr(s8) = G_IMPLICIT_DEF
; FAST: $al = COPY [[DEF]](s8)
; FAST: RET 0, implicit $al
; GREEDY-LABEL: name: test_undef
; GREEDY: [[DEF:%[0-9]+]]:gpr(s8) = G_IMPLICIT_DEF
; GREEDY: $al = COPY [[DEF]](s8)
; GREEDY: RET 0, implicit $al
%0(s8) = G_IMPLICIT_DEF
$al = COPY %0(s8)
RET 0, implicit $al
...
---
name: test_undef2
alignment: 4
legalized: true
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
- { id: 2, class: _, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
body: |
bb.1 (%ir-block.0):
liveins: $edi
; FAST-LABEL: name: test_undef2
; FAST: [[COPY:%[0-9]+]]:gpr(s8) = COPY $dil
; FAST: [[DEF:%[0-9]+]]:gpr(s8) = G_IMPLICIT_DEF
; FAST: [[ADD:%[0-9]+]]:gpr(s8) = G_ADD [[COPY]], [[DEF]]
; FAST: $al = COPY [[ADD]](s8)
; FAST: RET 0, implicit $al
; GREEDY-LABEL: name: test_undef2
; GREEDY: [[COPY:%[0-9]+]]:gpr(s8) = COPY $dil
; GREEDY: [[DEF:%[0-9]+]]:gpr(s8) = G_IMPLICIT_DEF
; GREEDY: [[ADD:%[0-9]+]]:gpr(s8) = G_ADD [[COPY]], [[DEF]]
; GREEDY: $al = COPY [[ADD]](s8)
; GREEDY: RET 0, implicit $al
%0(s8) = COPY $dil
%1(s8) = G_IMPLICIT_DEF
%2(s8) = G_ADD %0, %1
$al = COPY %2(s8)
RET 0, implicit $al
...
---
name: test_undef3
alignment: 4
legalized: true
regBankSelected: false
registers:
- { id: 1, class: _, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
body: |
bb.1 (%ir-block.0):
; FAST-LABEL: name: test_undef3
; FAST: [[DEF:%[0-9]+]]:vecr(s128) = G_IMPLICIT_DEF
; FAST: $xmm0 = COPY [[DEF]](s128)
; FAST: RET 0, implicit $xmm0
; GREEDY-LABEL: name: test_undef3
; GREEDY: [[DEF:%[0-9]+]]:vecr(s128) = G_IMPLICIT_DEF
; GREEDY: $xmm0 = COPY [[DEF]](s128)
; GREEDY: RET 0, implicit $xmm0
%1(s128) = G_IMPLICIT_DEF
$xmm0 = COPY %1(s128)
RET 0, implicit $xmm0
...
---
name: test_undef4
alignment: 4
legalized: true
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
- { id: 2, class: _, preferred-register: '' }
- { id: 3, class: _, preferred-register: '' }
- { id: 4, class: _, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
body: |
bb.1 (%ir-block.0):
liveins: $xmm0
; FAST-LABEL: name: test_undef4
; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
; FAST: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128)
; FAST: [[DEF:%[0-9]+]]:gpr(s32) = G_IMPLICIT_DEF
; FAST: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32)
; FAST: [[FADD:%[0-9]+]]:vecr(s32) = G_FADD [[TRUNC]], [[COPY1]]
; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FADD]](s32)
; FAST: $xmm0 = COPY [[ANYEXT]](s128)
; FAST: RET 0, implicit $xmm0
; GREEDY-LABEL: name: test_undef4
; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128)
; GREEDY: [[DEF:%[0-9]+]]:gpr(s32) = G_IMPLICIT_DEF
; GREEDY: [[COPY1:%[0-9]+]]:vecr(s32) = COPY [[DEF]](s32)
; GREEDY: [[FADD:%[0-9]+]]:vecr(s32) = G_FADD [[TRUNC]], [[COPY1]]
; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FADD]](s32)
; GREEDY: $xmm0 = COPY [[ANYEXT]](s128)
; GREEDY: RET 0, implicit $xmm0
%1:_(s128) = COPY $xmm0
%0:_(s32) = G_TRUNC %1(s128)
%2:_(s32) = G_IMPLICIT_DEF
%3:_(s32) = G_FADD %0, %2
%4:_(s128) = G_ANYEXT %3(s32)
$xmm0 = COPY %4(s128)
RET 0, implicit $xmm0
...
---
name: test_i32
alignment: 4
legalized: true
regBankSelected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
- { id: 2, class: _, preferred-register: '' }
- { id: 3, class: _, preferred-register: '' }
- { id: 4, class: _, preferred-register: '' }
- { id: 5, class: _, preferred-register: '' }
body: |
; FAST-LABEL: name: test_i32
; FAST: bb.0.entry:
; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; FAST: liveins: $edi, $edx, $esi
; FAST: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
; FAST: [[COPY1:%[0-9]+]]:gpr(s32) = COPY $esi
; FAST: [[COPY2:%[0-9]+]]:gpr(s32) = COPY $edx
; FAST: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
; FAST: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
; FAST: G_BRCOND [[ICMP]](s1), %bb.1
; FAST: G_BR %bb.2
; FAST: bb.1.cond.true:
; FAST: successors: %bb.3(0x80000000)
; FAST: G_BR %bb.3
; FAST: bb.2.cond.false:
; FAST: successors: %bb.3(0x80000000)
; FAST: bb.3.cond.end:
; FAST: [[PHI:%[0-9]+]]:gpr(s32) = G_PHI [[COPY1]](s32), %bb.1, [[COPY2]](s32), %bb.2
; FAST: $eax = COPY [[PHI]](s32)
; FAST: RET 0, implicit $eax
; GREEDY-LABEL: name: test_i32
; GREEDY: bb.0.entry:
; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GREEDY: liveins: $edi, $edx, $esi
; GREEDY: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
; GREEDY: [[COPY1:%[0-9]+]]:gpr(s32) = COPY $esi
; GREEDY: [[COPY2:%[0-9]+]]:gpr(s32) = COPY $edx
; GREEDY: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
; GREEDY: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
; GREEDY: G_BRCOND [[ICMP]](s1), %bb.1
; GREEDY: G_BR %bb.2
; GREEDY: bb.1.cond.true:
; GREEDY: successors: %bb.3(0x80000000)
; GREEDY: G_BR %bb.3
; GREEDY: bb.2.cond.false:
; GREEDY: successors: %bb.3(0x80000000)
; GREEDY: bb.3.cond.end:
; GREEDY: [[PHI:%[0-9]+]]:gpr(s32) = G_PHI [[COPY1]](s32), %bb.1, [[COPY2]](s32), %bb.2
; GREEDY: $eax = COPY [[PHI]](s32)
; GREEDY: RET 0, implicit $eax
bb.0.entry:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $edi, $edx, $esi
%0(s32) = COPY $edi
%1(s32) = COPY $esi
%2(s32) = COPY $edx
%3(s32) = G_CONSTANT i32 0
%4(s1) = G_ICMP intpred(sgt), %0(s32), %3
G_BRCOND %4(s1), %bb.1
G_BR %bb.2
bb.1.cond.true:
successors: %bb.3(0x80000000)
G_BR %bb.3
bb.2.cond.false:
successors: %bb.3(0x80000000)
bb.3.cond.end:
%5(s32) = G_PHI %1(s32), %bb.1, %2(s32), %bb.2
$eax = COPY %5(s32)
RET 0, implicit $eax
...
---
name: test_float
alignment: 4
legalized: true
regBankSelected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
- { id: 2, class: _, preferred-register: '' }
- { id: 3, class: _, preferred-register: '' }
- { id: 4, class: _, preferred-register: '' }
- { id: 5, class: _, preferred-register: '' }
body: |
; FAST-LABEL: name: test_float
; FAST: bb.0.entry:
; FAST: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; FAST: liveins: $edi, $xmm0, $xmm1
; FAST: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
; FAST: [[COPY1:%[0-9]+]]:vecr(s128) = COPY $xmm0
; FAST: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY1]](s128)
; FAST: [[COPY2:%[0-9]+]]:vecr(s128) = COPY $xmm1
; FAST: [[TRUNC1:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY2]](s128)
; FAST: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
; FAST: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
; FAST: G_BRCOND [[ICMP]](s1), %bb.2
; FAST: bb.1.cond.false:
; FAST: successors: %bb.2(0x80000000)
; FAST: bb.2.cond.end:
; FAST: [[PHI:%[0-9]+]]:vecr(s32) = G_PHI [[TRUNC1]](s32), %bb.1, [[TRUNC]](s32), %bb.0
; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[PHI]](s32)
; FAST: $xmm0 = COPY [[ANYEXT]](s128)
; FAST: RET 0, implicit $xmm0
; GREEDY-LABEL: name: test_float
; GREEDY: bb.0.entry:
; GREEDY: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; GREEDY: liveins: $edi, $xmm0, $xmm1
; GREEDY: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
; GREEDY: [[COPY1:%[0-9]+]]:vecr(s128) = COPY $xmm0
; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY1]](s128)
; GREEDY: [[COPY2:%[0-9]+]]:vecr(s128) = COPY $xmm1
; GREEDY: [[TRUNC1:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY2]](s128)
; GREEDY: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
; GREEDY: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
; GREEDY: G_BRCOND [[ICMP]](s1), %bb.2
; GREEDY: bb.1.cond.false:
; GREEDY: successors: %bb.2(0x80000000)
; GREEDY: bb.2.cond.end:
; GREEDY: [[PHI:%[0-9]+]]:vecr(s32) = G_PHI [[TRUNC1]](s32), %bb.1, [[TRUNC]](s32), %bb.0
; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[PHI]](s32)
; GREEDY: $xmm0 = COPY [[ANYEXT]](s128)
; GREEDY: RET 0, implicit $xmm0
bb.1.entry:
successors: %bb.3(0x40000000), %bb.2(0x40000000)
liveins: $edi, $xmm0, $xmm1
%0:_(s32) = COPY $edi
%3:_(s128) = COPY $xmm0
%1:_(s32) = G_TRUNC %3(s128)
%4:_(s128) = COPY $xmm1
%2:_(s32) = G_TRUNC %4(s128)
%5:_(s32) = G_CONSTANT i32 0
%6:_(s1) = G_ICMP intpred(sgt), %0(s32), %5
G_BRCOND %6(s1), %bb.3
bb.2.cond.false:
successors: %bb.3(0x80000000)
bb.3.cond.end:
%7:_(s32) = G_PHI %2(s32), %bb.2, %1(s32), %bb.1
%8:_(s128) = G_ANYEXT %7(s32)
$xmm0 = COPY %8(s128)
RET 0, implicit $xmm0
...
---
name: test_fpext
alignment: 4
legalized: true
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
body: |
bb.1.entry:
liveins: $xmm0
; FAST-LABEL: name: test_fpext
; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
; FAST: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128)
; FAST: [[FPEXT:%[0-9]+]]:vecr(s64) = G_FPEXT [[TRUNC]](s32)
; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FPEXT]](s64)
; FAST: $xmm0 = COPY [[ANYEXT]](s128)
; FAST: RET 0, implicit $xmm0
; GREEDY-LABEL: name: test_fpext
; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY]](s128)
; GREEDY: [[FPEXT:%[0-9]+]]:vecr(s64) = G_FPEXT [[TRUNC]](s32)
; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FPEXT]](s64)
; GREEDY: $xmm0 = COPY [[ANYEXT]](s128)
; GREEDY: RET 0, implicit $xmm0
%1:_(s128) = COPY $xmm0
%0:_(s32) = G_TRUNC %1(s128)
%2:_(s64) = G_FPEXT %0(s32)
%3:_(s128) = G_ANYEXT %2(s64)
$xmm0 = COPY %3(s128)
RET 0, implicit $xmm0
...
---
name: test_fptrunc
alignment: 4
legalized: true
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
body: |
bb.1.entry:
liveins: $xmm0
; FAST-LABEL: name: test_fptrunc
; FAST: liveins: $xmm0
; FAST: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
; FAST: [[TRUNC:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY]](s128)
; FAST: [[FPTRUNC:%[0-9]+]]:vecr(s32) = G_FPTRUNC [[TRUNC]](s64)
; FAST: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FPTRUNC]](s32)
; FAST: $xmm0 = COPY [[ANYEXT]](s128)
; FAST: RET 0, implicit $xmm0
; GREEDY-LABEL: name: test_fptrunc
; GREEDY: liveins: $xmm0
; GREEDY: [[COPY:%[0-9]+]]:vecr(s128) = COPY $xmm0
; GREEDY: [[TRUNC:%[0-9]+]]:vecr(s64) = G_TRUNC [[COPY]](s128)
; GREEDY: [[FPTRUNC:%[0-9]+]]:vecr(s32) = G_FPTRUNC [[TRUNC]](s64)
; GREEDY: [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[FPTRUNC]](s32)
; GREEDY: $xmm0 = COPY [[ANYEXT]](s128)
; GREEDY: RET 0, implicit $xmm0
%1:_(s128) = COPY $xmm0
%0:_(s64) = G_TRUNC %1(s128)
%2:_(s32) = G_FPTRUNC %0(s64)
%3:_(s128) = G_ANYEXT %2(s32)
$xmm0 = COPY %3(s128)
RET 0, implicit $xmm0
...
---
name: test_fconstant
# ALL-LABEL: name: test_fconstant
legalized: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
; FAST-LABEL: name: test_fconstant