test/CodeGen/RISCV/atomic-rmw.ll - llvm - Git at Google

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32IA %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64IA %s

 define i8 @atomicrmw_xchg_i8_monotonic(i8* %a, i8 %b) {
 ; RV32I-LABEL: atomicrmw_xchg_i8_monotonic:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    mv a2, zero
 ; RV32I-NEXT:    call __atomic_exchange_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_xchg_i8_monotonic:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 255
 ; RV32IA-NEXT:    sll a3, a3, a2
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w a4, (a0)
 ; RV32IA-NEXT:    add a5, zero, a1
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    sc.w a5, a5, (a0)
 ; RV32IA-NEXT:    bnez a5, .LBB0_1
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_xchg_i8_monotonic:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    mv a2, zero
 ; RV64I-NEXT:    call __atomic_exchange_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_xchg_i8_monotonic:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 255
 ; RV64IA-NEXT:    sllw a3, a3, a2
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w a4, (a0)
 ; RV64IA-NEXT:    add a5, zero, a1
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    sc.w a5, a5, (a0)
 ; RV64IA-NEXT:    bnez a5, .LBB0_1
 ; RV64IA-NEXT:  # %bb.2:
 ; RV64IA-NEXT:    srlw a0, a4, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw xchg i8* %a, i8 %b monotonic
   ret i8 %1
 }

 define i8 @atomicrmw_xchg_i8_acquire(i8* %a, i8 %b) {
 ; RV32I-LABEL: atomicrmw_xchg_i8_acquire:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 2
 ; RV32I-NEXT:    call __atomic_exchange_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_xchg_i8_acquire:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 255
 ; RV32IA-NEXT:    sll a3, a3, a2
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB1_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w.aq a4, (a0)
 ; RV32IA-NEXT:    add a5, zero, a1
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    sc.w a5, a5, (a0)
 ; RV32IA-NEXT:    bnez a5, .LBB1_1
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_xchg_i8_acquire:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a2, zero, 2
 ; RV64I-NEXT:    call __atomic_exchange_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_xchg_i8_acquire:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 255
 ; RV64IA-NEXT:    sllw a3, a3, a2
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB1_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w.aq a4, (a0)
 ; RV64IA-NEXT:    add a5, zero, a1
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    sc.w a5, a5, (a0)
 ; RV64IA-NEXT:    bnez a5, .LBB1_1
 ; RV64IA-NEXT:  # %bb.2:
 ; RV64IA-NEXT:    srlw a0, a4, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw xchg i8* %a, i8 %b acquire
   ret i8 %1
 }

 define i8 @atomicrmw_xchg_i8_release(i8* %a, i8 %b) {
 ; RV32I-LABEL: atomicrmw_xchg_i8_release:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 3
 ; RV32I-NEXT:    call __atomic_exchange_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_xchg_i8_release:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 255
 ; RV32IA-NEXT:    sll a3, a3, a2
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB2_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w a4, (a0)
 ; RV32IA-NEXT:    add a5, zero, a1
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    sc.w.rl a5, a5, (a0)
 ; RV32IA-NEXT:    bnez a5, .LBB2_1
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_xchg_i8_release:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a2, zero, 3
 ; RV64I-NEXT:    call __atomic_exchange_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_xchg_i8_release:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 255
 ; RV64IA-NEXT:    sllw a3, a3, a2
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB2_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w a4, (a0)
 ; RV64IA-NEXT:    add a5, zero, a1
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
 ; RV64IA-NEXT:    bnez a5, .LBB2_1
 ; RV64IA-NEXT:  # %bb.2:
 ; RV64IA-NEXT:    srlw a0, a4, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw xchg i8* %a, i8 %b release
   ret i8 %1
 }

 define i8 @atomicrmw_xchg_i8_acq_rel(i8* %a, i8 %b) {
 ; RV32I-LABEL: atomicrmw_xchg_i8_acq_rel:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 4
 ; RV32I-NEXT:    call __atomic_exchange_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_xchg_i8_acq_rel:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 255
 ; RV32IA-NEXT:    sll a3, a3, a2
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB3_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w.aq a4, (a0)
 ; RV32IA-NEXT:    add a5, zero, a1
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    sc.w.rl a5, a5, (a0)
 ; RV32IA-NEXT:    bnez a5, .LBB3_1
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_xchg_i8_acq_rel:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a2, zero, 4
 ; RV64I-NEXT:    call __atomic_exchange_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_xchg_i8_acq_rel:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 255
 ; RV64IA-NEXT:    sllw a3, a3, a2
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB3_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w.aq a4, (a0)
 ; RV64IA-NEXT:    add a5, zero, a1
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
 ; RV64IA-NEXT:    bnez a5, .LBB3_1
 ; RV64IA-NEXT:  # %bb.2:
 ; RV64IA-NEXT:    srlw a0, a4, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw xchg i8* %a, i8 %b acq_rel
   ret i8 %1
 }

 define i8 @atomicrmw_xchg_i8_seq_cst(i8* %a, i8 %b) {
 ; RV32I-LABEL: atomicrmw_xchg_i8_seq_cst:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 5
 ; RV32I-NEXT:    call __atomic_exchange_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_xchg_i8_seq_cst:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 255
 ; RV32IA-NEXT:    sll a3, a3, a2
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB4_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w.aqrl a4, (a0)
 ; RV32IA-NEXT:    add a5, zero, a1
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    sc.w.aqrl a5, a5, (a0)
 ; RV32IA-NEXT:    bnez a5, .LBB4_1
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_xchg_i8_seq_cst:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a2, zero, 5
 ; RV64I-NEXT:    call __atomic_exchange_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_xchg_i8_seq_cst:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 255
 ; RV64IA-NEXT:    sllw a3, a3, a2
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB4_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w.aqrl a4, (a0)
 ; RV64IA-NEXT:    add a5, zero, a1
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    sc.w.aqrl a5, a5, (a0)
 ; RV64IA-NEXT:    bnez a5, .LBB4_1
 ; RV64IA-NEXT:  # %bb.2:
 ; RV64IA-NEXT:    srlw a0, a4, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw xchg i8* %a, i8 %b seq_cst
   ret i8 %1
 }

 define i8 @atomicrmw_add_i8_monotonic(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_add_i8_monotonic:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    mv a2, zero
 ; RV32I-NEXT:    call __atomic_fetch_add_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_add_i8_monotonic:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 255
 ; RV32IA-NEXT:    sll a3, a3, a2
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB5_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w a4, (a0)
 ; RV32IA-NEXT:    add a5, a4, a1
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    sc.w a5, a5, (a0)
 ; RV32IA-NEXT:    bnez a5, .LBB5_1
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_add_i8_monotonic:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    mv a2, zero
 ; RV64I-NEXT:    call __atomic_fetch_add_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_add_i8_monotonic:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 255
 ; RV64IA-NEXT:    sllw a3, a3, a2
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB5_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w a4, (a0)
 ; RV64IA-NEXT:    add a5, a4, a1
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    sc.w a5, a5, (a0)
 ; RV64IA-NEXT:    bnez a5, .LBB5_1
 ; RV64IA-NEXT:  # %bb.2:
 ; RV64IA-NEXT:    srlw a0, a4, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw add i8* %a, i8 %b monotonic
   ret i8 %1
 }

 define i8 @atomicrmw_add_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_add_i8_acquire:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 2
 ; RV32I-NEXT:    call __atomic_fetch_add_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_add_i8_acquire:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 255
 ; RV32IA-NEXT:    sll a3, a3, a2
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB6_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w.aq a4, (a0)
 ; RV32IA-NEXT:    add a5, a4, a1
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    sc.w a5, a5, (a0)
 ; RV32IA-NEXT:    bnez a5, .LBB6_1
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_add_i8_acquire:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a2, zero, 2
 ; RV64I-NEXT:    call __atomic_fetch_add_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_add_i8_acquire:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 255
 ; RV64IA-NEXT:    sllw a3, a3, a2
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB6_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w.aq a4, (a0)
 ; RV64IA-NEXT:    add a5, a4, a1
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    sc.w a5, a5, (a0)
 ; RV64IA-NEXT:    bnez a5, .LBB6_1
 ; RV64IA-NEXT:  # %bb.2:
 ; RV64IA-NEXT:    srlw a0, a4, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw add i8* %a, i8 %b acquire
   ret i8 %1
 }

 define i8 @atomicrmw_add_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_add_i8_release:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 3
 ; RV32I-NEXT:    call __atomic_fetch_add_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_add_i8_release:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 255
 ; RV32IA-NEXT:    sll a3, a3, a2
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB7_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w a4, (a0)
 ; RV32IA-NEXT:    add a5, a4, a1
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    sc.w.rl a5, a5, (a0)
 ; RV32IA-NEXT:    bnez a5, .LBB7_1
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_add_i8_release:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a2, zero, 3
 ; RV64I-NEXT:    call __atomic_fetch_add_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_add_i8_release:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 255
 ; RV64IA-NEXT:    sllw a3, a3, a2
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB7_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w a4, (a0)
 ; RV64IA-NEXT:    add a5, a4, a1
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
 ; RV64IA-NEXT:    bnez a5, .LBB7_1
 ; RV64IA-NEXT:  # %bb.2:
 ; RV64IA-NEXT:    srlw a0, a4, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw add i8* %a, i8 %b release
   ret i8 %1
 }

 define i8 @atomicrmw_add_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_add_i8_acq_rel:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 4
 ; RV32I-NEXT:    call __atomic_fetch_add_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_add_i8_acq_rel:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 255
 ; RV32IA-NEXT:    sll a3, a3, a2
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB8_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w.aq a4, (a0)
 ; RV32IA-NEXT:    add a5, a4, a1
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    sc.w.rl a5, a5, (a0)
 ; RV32IA-NEXT:    bnez a5, .LBB8_1
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_add_i8_acq_rel:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a2, zero, 4
 ; RV64I-NEXT:    call __atomic_fetch_add_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_add_i8_acq_rel:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 255
 ; RV64IA-NEXT:    sllw a3, a3, a2
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB8_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w.aq a4, (a0)
 ; RV64IA-NEXT:    add a5, a4, a1
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
 ; RV64IA-NEXT:    bnez a5, .LBB8_1
 ; RV64IA-NEXT:  # %bb.2:
 ; RV64IA-NEXT:    srlw a0, a4, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw add i8* %a, i8 %b acq_rel
   ret i8 %1
 }

 define i8 @atomicrmw_add_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_add_i8_seq_cst:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 5
 ; RV32I-NEXT:    call __atomic_fetch_add_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_add_i8_seq_cst:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 255
 ; RV32IA-NEXT:    sll a3, a3, a2
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB9_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w.aqrl a4, (a0)
 ; RV32IA-NEXT:    add a5, a4, a1
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    sc.w.aqrl a5, a5, (a0)
 ; RV32IA-NEXT:    bnez a5, .LBB9_1
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_add_i8_seq_cst:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a2, zero, 5
 ; RV64I-NEXT:    call __atomic_fetch_add_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_add_i8_seq_cst:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 255
 ; RV64IA-NEXT:    sllw a3, a3, a2
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB9_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w.aqrl a4, (a0)
 ; RV64IA-NEXT:    add a5, a4, a1
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    sc.w.aqrl a5, a5, (a0)
 ; RV64IA-NEXT:    bnez a5, .LBB9_1
 ; RV64IA-NEXT:  # %bb.2:
 ; RV64IA-NEXT:    srlw a0, a4, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw add i8* %a, i8 %b seq_cst
   ret i8 %1
 }

 define i8 @atomicrmw_sub_i8_monotonic(i8* %a, i8 %b) {
 ; RV32I-LABEL: atomicrmw_sub_i8_monotonic:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    mv a2, zero
 ; RV32I-NEXT:    call __atomic_fetch_sub_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_sub_i8_monotonic:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 255
 ; RV32IA-NEXT:    sll a3, a3, a2
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB10_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w a4, (a0)
 ; RV32IA-NEXT:    sub a5, a4, a1
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    sc.w a5, a5, (a0)
 ; RV32IA-NEXT:    bnez a5, .LBB10_1
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_sub_i8_monotonic:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    mv a2, zero
 ; RV64I-NEXT:    call __atomic_fetch_sub_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_sub_i8_monotonic:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 255
 ; RV64IA-NEXT:    sllw a3, a3, a2
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB10_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w a4, (a0)
 ; RV64IA-NEXT:    sub a5, a4, a1
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    sc.w a5, a5, (a0)
 ; RV64IA-NEXT:    bnez a5, .LBB10_1
 ; RV64IA-NEXT:  # %bb.2:
 ; RV64IA-NEXT:    srlw a0, a4, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw sub i8* %a, i8 %b monotonic
   ret i8 %1
 }

 define i8 @atomicrmw_sub_i8_acquire(i8* %a, i8 %b) {
 ; RV32I-LABEL: atomicrmw_sub_i8_acquire:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 2
 ; RV32I-NEXT:    call __atomic_fetch_sub_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_sub_i8_acquire:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 255
 ; RV32IA-NEXT:    sll a3, a3, a2
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB11_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w.aq a4, (a0)
 ; RV32IA-NEXT:    sub a5, a4, a1
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    sc.w a5, a5, (a0)
 ; RV32IA-NEXT:    bnez a5, .LBB11_1
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_sub_i8_acquire:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a2, zero, 2
 ; RV64I-NEXT:    call __atomic_fetch_sub_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_sub_i8_acquire:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 255
 ; RV64IA-NEXT:    sllw a3, a3, a2
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB11_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w.aq a4, (a0)
 ; RV64IA-NEXT:    sub a5, a4, a1
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    sc.w a5, a5, (a0)
 ; RV64IA-NEXT:    bnez a5, .LBB11_1
 ; RV64IA-NEXT:  # %bb.2:
 ; RV64IA-NEXT:    srlw a0, a4, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw sub i8* %a, i8 %b acquire
   ret i8 %1
 }

 define i8 @atomicrmw_sub_i8_release(i8* %a, i8 %b) {
 ; RV32I-LABEL: atomicrmw_sub_i8_release:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 3
 ; RV32I-NEXT:    call __atomic_fetch_sub_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_sub_i8_release:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 255
 ; RV32IA-NEXT:    sll a3, a3, a2
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB12_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w a4, (a0)
 ; RV32IA-NEXT:    sub a5, a4, a1
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    sc.w.rl a5, a5, (a0)
 ; RV32IA-NEXT:    bnez a5, .LBB12_1
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_sub_i8_release:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a2, zero, 3
 ; RV64I-NEXT:    call __atomic_fetch_sub_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_sub_i8_release:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 255
 ; RV64IA-NEXT:    sllw a3, a3, a2
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB12_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w a4, (a0)
 ; RV64IA-NEXT:    sub a5, a4, a1
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
 ; RV64IA-NEXT:    bnez a5, .LBB12_1
 ; RV64IA-NEXT:  # %bb.2:
 ; RV64IA-NEXT:    srlw a0, a4, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw sub i8* %a, i8 %b release
   ret i8 %1
 }

 define i8 @atomicrmw_sub_i8_acq_rel(i8* %a, i8 %b) {
 ; RV32I-LABEL: atomicrmw_sub_i8_acq_rel:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 4
 ; RV32I-NEXT:    call __atomic_fetch_sub_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_sub_i8_acq_rel:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 255
 ; RV32IA-NEXT:    sll a3, a3, a2
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB13_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w.aq a4, (a0)
 ; RV32IA-NEXT:    sub a5, a4, a1
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    sc.w.rl a5, a5, (a0)
 ; RV32IA-NEXT:    bnez a5, .LBB13_1
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_sub_i8_acq_rel:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a2, zero, 4
 ; RV64I-NEXT:    call __atomic_fetch_sub_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_sub_i8_acq_rel:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 255
 ; RV64IA-NEXT:    sllw a3, a3, a2
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB13_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w.aq a4, (a0)
 ; RV64IA-NEXT:    sub a5, a4, a1
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
 ; RV64IA-NEXT:    bnez a5, .LBB13_1
 ; RV64IA-NEXT:  # %bb.2:
 ; RV64IA-NEXT:    srlw a0, a4, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw sub i8* %a, i8 %b acq_rel
   ret i8 %1
 }

 define i8 @atomicrmw_sub_i8_seq_cst(i8* %a, i8 %b) {
 ; RV32I-LABEL: atomicrmw_sub_i8_seq_cst:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 5
 ; RV32I-NEXT:    call __atomic_fetch_sub_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_sub_i8_seq_cst:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 255
 ; RV32IA-NEXT:    sll a3, a3, a2
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB14_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w.aqrl a4, (a0)
 ; RV32IA-NEXT:    sub a5, a4, a1
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    sc.w.aqrl a5, a5, (a0)
 ; RV32IA-NEXT:    bnez a5, .LBB14_1
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_sub_i8_seq_cst:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a2, zero, 5
 ; RV64I-NEXT:    call __atomic_fetch_sub_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_sub_i8_seq_cst:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 255
 ; RV64IA-NEXT:    sllw a3, a3, a2
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB14_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w.aqrl a4, (a0)
 ; RV64IA-NEXT:    sub a5, a4, a1
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    sc.w.aqrl a5, a5, (a0)
 ; RV64IA-NEXT:    bnez a5, .LBB14_1
 ; RV64IA-NEXT:  # %bb.2:
 ; RV64IA-NEXT:    srlw a0, a4, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw sub i8* %a, i8 %b seq_cst
   ret i8 %1
 }

 define i8 @atomicrmw_and_i8_monotonic(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_and_i8_monotonic:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    mv a2, zero
 ; RV32I-NEXT:    call __atomic_fetch_and_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_and_i8_monotonic:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    addi a3, zero, 255
 ; RV32IA-NEXT:    sll a3, a3, a2
 ; RV32IA-NEXT:    not a3, a3
 ; RV32IA-NEXT:    or a1, a3, a1
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:    amoand.w a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_and_i8_monotonic:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    mv a2, zero
 ; RV64I-NEXT:    call __atomic_fetch_and_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_and_i8_monotonic:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    addi a3, zero, 255
 ; RV64IA-NEXT:    sllw a3, a3, a2
 ; RV64IA-NEXT:    not a3, a3
 ; RV64IA-NEXT:    or a1, a3, a1
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:    amoand.w a0, a1, (a0)
 ; RV64IA-NEXT:    srlw a0, a0, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw and i8* %a, i8 %b monotonic
   ret i8 %1
 }

 define i8 @atomicrmw_and_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_and_i8_acquire:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 2
 ; RV32I-NEXT:    call __atomic_fetch_and_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_and_i8_acquire:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    addi a3, zero, 255
 ; RV32IA-NEXT:    sll a3, a3, a2
 ; RV32IA-NEXT:    not a3, a3
 ; RV32IA-NEXT:    or a1, a3, a1
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:    amoand.w.aq a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_and_i8_acquire:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a2, zero, 2
 ; RV64I-NEXT:    call __atomic_fetch_and_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_and_i8_acquire:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    addi a3, zero, 255
 ; RV64IA-NEXT:    sllw a3, a3, a2
 ; RV64IA-NEXT:    not a3, a3
 ; RV64IA-NEXT:    or a1, a3, a1
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:    amoand.w.aq a0, a1, (a0)
 ; RV64IA-NEXT:    srlw a0, a0, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw and i8* %a, i8 %b acquire
   ret i8 %1
 }

 define i8 @atomicrmw_and_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_and_i8_release:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 3
 ; RV32I-NEXT:    call __atomic_fetch_and_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_and_i8_release:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    addi a3, zero, 255
 ; RV32IA-NEXT:    sll a3, a3, a2
 ; RV32IA-NEXT:    not a3, a3
 ; RV32IA-NEXT:    or a1, a3, a1
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:    amoand.w.rl a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_and_i8_release:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a2, zero, 3
 ; RV64I-NEXT:    call __atomic_fetch_and_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_and_i8_release:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    addi a3, zero, 255
 ; RV64IA-NEXT:    sllw a3, a3, a2
 ; RV64IA-NEXT:    not a3, a3
 ; RV64IA-NEXT:    or a1, a3, a1
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:    amoand.w.rl a0, a1, (a0)
 ; RV64IA-NEXT:    srlw a0, a0, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw and i8* %a, i8 %b release
   ret i8 %1
 }

 define i8 @atomicrmw_and_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_and_i8_acq_rel:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 4
 ; RV32I-NEXT:    call __atomic_fetch_and_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_and_i8_acq_rel:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    addi a3, zero, 255
 ; RV32IA-NEXT:    sll a3, a3, a2
 ; RV32IA-NEXT:    not a3, a3
 ; RV32IA-NEXT:    or a1, a3, a1
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:    amoand.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_and_i8_acq_rel:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a2, zero, 4
 ; RV64I-NEXT:    call __atomic_fetch_and_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_and_i8_acq_rel:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    addi a3, zero, 255
 ; RV64IA-NEXT:    sllw a3, a3, a2
 ; RV64IA-NEXT:    not a3, a3
 ; RV64IA-NEXT:    or a1, a3, a1
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:    amoand.w.aqrl a0, a1, (a0)
 ; RV64IA-NEXT:    srlw a0, a0, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw and i8* %a, i8 %b acq_rel
   ret i8 %1
 }

 define i8 @atomicrmw_and_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_and_i8_seq_cst:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 5
 ; RV32I-NEXT:    call __atomic_fetch_and_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_and_i8_seq_cst:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    addi a3, zero, 255
 ; RV32IA-NEXT:    sll a3, a3, a2
 ; RV32IA-NEXT:    not a3, a3
 ; RV32IA-NEXT:    or a1, a3, a1
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:    amoand.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_and_i8_seq_cst:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a2, zero, 5
 ; RV64I-NEXT:    call __atomic_fetch_and_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_and_i8_seq_cst:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    addi a3, zero, 255
 ; RV64IA-NEXT:    sllw a3, a3, a2
 ; RV64IA-NEXT:    not a3, a3
 ; RV64IA-NEXT:    or a1, a3, a1
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:    amoand.w.aqrl a0, a1, (a0)
 ; RV64IA-NEXT:    srlw a0, a0, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw and i8* %a, i8 %b seq_cst
   ret i8 %1
 }

 define i8 @atomicrmw_nand_i8_monotonic(i8* %a, i8 %b) {
 ; RV32I-LABEL: atomicrmw_nand_i8_monotonic:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    mv a2, zero
 ; RV32I-NEXT:    call __atomic_fetch_nand_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_nand_i8_monotonic:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 255
 ; RV32IA-NEXT:    sll a3, a3, a2
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB20_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w a4, (a0)
 ; RV32IA-NEXT:    and a5, a4, a1
 ; RV32IA-NEXT:    not a5, a5
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    sc.w a5, a5, (a0)
 ; RV32IA-NEXT:    bnez a5, .LBB20_1
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_nand_i8_monotonic:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    mv a2, zero
 ; RV64I-NEXT:    call __atomic_fetch_nand_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_nand_i8_monotonic:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 255
 ; RV64IA-NEXT:    sllw a3, a3, a2
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB20_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w a4, (a0)
 ; RV64IA-NEXT:    and a5, a4, a1
 ; RV64IA-NEXT:    not a5, a5
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    sc.w a5, a5, (a0)
 ; RV64IA-NEXT:    bnez a5, .LBB20_1
 ; RV64IA-NEXT:  # %bb.2:
 ; RV64IA-NEXT:    srlw a0, a4, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw nand i8* %a, i8 %b monotonic
   ret i8 %1
 }

 define i8 @atomicrmw_nand_i8_acquire(i8* %a, i8 %b) {
 ; RV32I-LABEL: atomicrmw_nand_i8_acquire:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 2
 ; RV32I-NEXT:    call __atomic_fetch_nand_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_nand_i8_acquire:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 255
 ; RV32IA-NEXT:    sll a3, a3, a2
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB21_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w.aq a4, (a0)
 ; RV32IA-NEXT:    and a5, a4, a1
 ; RV32IA-NEXT:    not a5, a5
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    sc.w a5, a5, (a0)
 ; RV32IA-NEXT:    bnez a5, .LBB21_1
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_nand_i8_acquire:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a2, zero, 2
 ; RV64I-NEXT:    call __atomic_fetch_nand_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_nand_i8_acquire:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 255
 ; RV64IA-NEXT:    sllw a3, a3, a2
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB21_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w.aq a4, (a0)
 ; RV64IA-NEXT:    and a5, a4, a1
 ; RV64IA-NEXT:    not a5, a5
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    sc.w a5, a5, (a0)
 ; RV64IA-NEXT:    bnez a5, .LBB21_1
 ; RV64IA-NEXT:  # %bb.2:
 ; RV64IA-NEXT:    srlw a0, a4, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw nand i8* %a, i8 %b acquire
   ret i8 %1
 }

 define i8 @atomicrmw_nand_i8_release(i8* %a, i8 %b) {
 ; RV32I-LABEL: atomicrmw_nand_i8_release:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 3
 ; RV32I-NEXT:    call __atomic_fetch_nand_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_nand_i8_release:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 255
 ; RV32IA-NEXT:    sll a3, a3, a2
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB22_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w a4, (a0)
 ; RV32IA-NEXT:    and a5, a4, a1
 ; RV32IA-NEXT:    not a5, a5
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    sc.w.rl a5, a5, (a0)
 ; RV32IA-NEXT:    bnez a5, .LBB22_1
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_nand_i8_release:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a2, zero, 3
 ; RV64I-NEXT:    call __atomic_fetch_nand_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_nand_i8_release:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 255
 ; RV64IA-NEXT:    sllw a3, a3, a2
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB22_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w a4, (a0)
 ; RV64IA-NEXT:    and a5, a4, a1
 ; RV64IA-NEXT:    not a5, a5
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
 ; RV64IA-NEXT:    bnez a5, .LBB22_1
 ; RV64IA-NEXT:  # %bb.2:
 ; RV64IA-NEXT:    srlw a0, a4, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw nand i8* %a, i8 %b release
   ret i8 %1
 }

 define i8 @atomicrmw_nand_i8_acq_rel(i8* %a, i8 %b) {
 ; RV32I-LABEL: atomicrmw_nand_i8_acq_rel:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 4
 ; RV32I-NEXT:    call __atomic_fetch_nand_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_nand_i8_acq_rel:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 255
 ; RV32IA-NEXT:    sll a3, a3, a2
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB23_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w.aq a4, (a0)
 ; RV32IA-NEXT:    and a5, a4, a1
 ; RV32IA-NEXT:    not a5, a5
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    sc.w.rl a5, a5, (a0)
 ; RV32IA-NEXT:    bnez a5, .LBB23_1
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_nand_i8_acq_rel:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a2, zero, 4
 ; RV64I-NEXT:    call __atomic_fetch_nand_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_nand_i8_acq_rel:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 255
 ; RV64IA-NEXT:    sllw a3, a3, a2
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB23_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w.aq a4, (a0)
 ; RV64IA-NEXT:    and a5, a4, a1
 ; RV64IA-NEXT:    not a5, a5
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
 ; RV64IA-NEXT:    bnez a5, .LBB23_1
 ; RV64IA-NEXT:  # %bb.2:
 ; RV64IA-NEXT:    srlw a0, a4, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw nand i8* %a, i8 %b acq_rel
   ret i8 %1
 }

 define i8 @atomicrmw_nand_i8_seq_cst(i8* %a, i8 %b) {
 ; RV32I-LABEL: atomicrmw_nand_i8_seq_cst:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 5
 ; RV32I-NEXT:    call __atomic_fetch_nand_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_nand_i8_seq_cst:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 255
 ; RV32IA-NEXT:    sll a3, a3, a2
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB24_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w.aqrl a4, (a0)
 ; RV32IA-NEXT:    and a5, a4, a1
 ; RV32IA-NEXT:    not a5, a5
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
 ; RV32IA-NEXT:    sc.w.aqrl a5, a5, (a0)
 ; RV32IA-NEXT:    bnez a5, .LBB24_1
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_nand_i8_seq_cst:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a2, zero, 5
 ; RV64I-NEXT:    call __atomic_fetch_nand_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_nand_i8_seq_cst:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 255
 ; RV64IA-NEXT:    sllw a3, a3, a2
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB24_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w.aqrl a4, (a0)
 ; RV64IA-NEXT:    and a5, a4, a1
 ; RV64IA-NEXT:    not a5, a5
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
 ; RV64IA-NEXT:    sc.w.aqrl a5, a5, (a0)
 ; RV64IA-NEXT:    bnez a5, .LBB24_1
 ; RV64IA-NEXT:  # %bb.2:
 ; RV64IA-NEXT:    srlw a0, a4, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw nand i8* %a, i8 %b seq_cst
   ret i8 %1
 }

 define i8 @atomicrmw_or_i8_monotonic(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_or_i8_monotonic:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    mv a2, zero
 ; RV32I-NEXT:    call __atomic_fetch_or_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_or_i8_monotonic:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:    amoor.w a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_or_i8_monotonic:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    mv a2, zero
 ; RV64I-NEXT:    call __atomic_fetch_or_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_or_i8_monotonic:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:    amoor.w a0, a1, (a0)
 ; RV64IA-NEXT:    srlw a0, a0, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw or i8* %a, i8 %b monotonic
   ret i8 %1
 }

 define i8 @atomicrmw_or_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_or_i8_acquire:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 2
 ; RV32I-NEXT:    call __atomic_fetch_or_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_or_i8_acquire:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:    amoor.w.aq a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_or_i8_acquire:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a2, zero, 2
 ; RV64I-NEXT:    call __atomic_fetch_or_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_or_i8_acquire:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:    amoor.w.aq a0, a1, (a0)
 ; RV64IA-NEXT:    srlw a0, a0, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw or i8* %a, i8 %b acquire
   ret i8 %1
 }

 define i8 @atomicrmw_or_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_or_i8_release:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 3
 ; RV32I-NEXT:    call __atomic_fetch_or_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_or_i8_release:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:    amoor.w.rl a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_or_i8_release:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a2, zero, 3
 ; RV64I-NEXT:    call __atomic_fetch_or_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_or_i8_release:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:    amoor.w.rl a0, a1, (a0)
 ; RV64IA-NEXT:    srlw a0, a0, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw or i8* %a, i8 %b release
   ret i8 %1
 }

 define i8 @atomicrmw_or_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_or_i8_acq_rel:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 4
 ; RV32I-NEXT:    call __atomic_fetch_or_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_or_i8_acq_rel:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:    amoor.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_or_i8_acq_rel:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a2, zero, 4
 ; RV64I-NEXT:    call __atomic_fetch_or_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_or_i8_acq_rel:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:    amoor.w.aqrl a0, a1, (a0)
 ; RV64IA-NEXT:    srlw a0, a0, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw or i8* %a, i8 %b acq_rel
   ret i8 %1
 }

 define i8 @atomicrmw_or_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_or_i8_seq_cst:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 5
 ; RV32I-NEXT:    call __atomic_fetch_or_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_or_i8_seq_cst:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:    amoor.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_or_i8_seq_cst:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a2, zero, 5
 ; RV64I-NEXT:    call __atomic_fetch_or_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_or_i8_seq_cst:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:    amoor.w.aqrl a0, a1, (a0)
 ; RV64IA-NEXT:    srlw a0, a0, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw or i8* %a, i8 %b seq_cst
   ret i8 %1
 }

 define i8 @atomicrmw_xor_i8_monotonic(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xor_i8_monotonic:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    mv a2, zero
 ; RV32I-NEXT:    call __atomic_fetch_xor_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_xor_i8_monotonic:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:    amoxor.w a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_xor_i8_monotonic:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    mv a2, zero
 ; RV64I-NEXT:    call __atomic_fetch_xor_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_xor_i8_monotonic:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:    amoxor.w a0, a1, (a0)
 ; RV64IA-NEXT:    srlw a0, a0, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw xor i8* %a, i8 %b monotonic
   ret i8 %1
 }

 define i8 @atomicrmw_xor_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xor_i8_acquire:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 2
 ; RV32I-NEXT:    call __atomic_fetch_xor_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_xor_i8_acquire:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:    amoxor.w.aq a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_xor_i8_acquire:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a2, zero, 2
 ; RV64I-NEXT:    call __atomic_fetch_xor_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_xor_i8_acquire:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:    amoxor.w.aq a0, a1, (a0)
 ; RV64IA-NEXT:    srlw a0, a0, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw xor i8* %a, i8 %b acquire
   ret i8 %1
 }

 define i8 @atomicrmw_xor_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xor_i8_release:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 3
 ; RV32I-NEXT:    call __atomic_fetch_xor_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_xor_i8_release:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:    amoxor.w.rl a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_xor_i8_release:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a2, zero, 3
 ; RV64I-NEXT:    call __atomic_fetch_xor_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_xor_i8_release:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:    amoxor.w.rl a0, a1, (a0)
 ; RV64IA-NEXT:    srlw a0, a0, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw xor i8* %a, i8 %b release
   ret i8 %1
 }

 define i8 @atomicrmw_xor_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xor_i8_acq_rel:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 4
 ; RV32I-NEXT:    call __atomic_fetch_xor_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_xor_i8_acq_rel:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:    amoxor.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_xor_i8_acq_rel:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a2, zero, 4
 ; RV64I-NEXT:    call __atomic_fetch_xor_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_xor_i8_acq_rel:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:    amoxor.w.aqrl a0, a1, (a0)
 ; RV64IA-NEXT:    srlw a0, a0, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw xor i8* %a, i8 %b acq_rel
   ret i8 %1
 }

 define i8 @atomicrmw_xor_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xor_i8_seq_cst:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    addi a2, zero, 5
 ; RV32I-NEXT:    call __atomic_fetch_xor_1
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_xor_i8_seq_cst:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    andi a1, a1, 255
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:    amoxor.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_xor_i8_seq_cst:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp)
 ; RV64I-NEXT:    addi a2, zero, 5
 ; RV64I-NEXT:    call __atomic_fetch_xor_1
 ; RV64I-NEXT:    ld ra, 8(sp)
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_xor_i8_seq_cst:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    andi a1, a1, 255
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:    amoxor.w.aqrl a0, a1, (a0)
 ; RV64IA-NEXT:    srlw a0, a0, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw xor i8* %a, i8 %b seq_cst
   ret i8 %1
 }

 define i8 @atomicrmw_max_i8_monotonic(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_max_i8_monotonic:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
 ; RV32I-NEXT:    sw s1, 24(sp)
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 24
 ; RV32I-NEXT:    srai s1, a1, 24
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB35_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 24
 ; RV32I-NEXT:    srai a1, a1, 24
 ; RV32I-NEXT:    mv a2, a0
 ; RV32I-NEXT:    blt s1, a1, .LBB35_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB35_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB35_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB35_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
 ; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    mv a3, zero
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_1
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB35_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
 ; RV32I-NEXT:    lw s1, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_max_i8_monotonic:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 24
 ; RV32IA-NEXT:    sub a6, a3, a2
 ; RV32IA-NEXT:    addi a4, zero, 255
 ; RV32IA-NEXT:    sll a7, a4, a2
 ; RV32IA-NEXT:    slli a1, a1, 24
 ; RV32IA-NEXT:    srai a1, a1, 24
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB35_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w a5, (a0)
 ; RV32IA-NEXT:    and a4, a5, a7
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    sll a4, a4, a6
 ; RV32IA-NEXT:    sra a4, a4, a6
 ; RV32IA-NEXT:    bge a4, a1, .LBB35_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB35_1 Depth=1
 ; RV32IA-NEXT:    xor a3, a5, a1
 ; RV32IA-NEXT:    and a3, a3, a7
 ; RV32IA-NEXT:    xor a3, a5, a3
 ; RV32IA-NEXT:  .LBB35_3: # in Loop: Header=BB35_1 Depth=1
 ; RV32IA-NEXT:    sc.w a3, a3, (a0)
 ; RV32IA-NEXT:    bnez a3, .LBB35_1
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_max_i8_monotonic:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s1, 32(sp)
 ; RV64I-NEXT:    sd s2, 24(sp)
 ; RV64I-NEXT:    sd s3, 16(sp)
 ; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 56
 ; RV64I-NEXT:    srai s1, a1, 56
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB35_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 56
 ; RV64I-NEXT:    srai a1, a1, 56
 ; RV64I-NEXT:    mv a2, a0
 ; RV64I-NEXT:    blt s1, a1, .LBB35_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB35_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB35_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB35_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    mv a3, zero
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    call __atomic_compare_exchange_1
 ; RV64I-NEXT:    mv a1, a0
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB35_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    ld s4, 8(sp)
 ; RV64I-NEXT:    ld s3, 16(sp)
 ; RV64I-NEXT:    ld s2, 24(sp)
 ; RV64I-NEXT:    ld s1, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_max_i8_monotonic:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 56
 ; RV64IA-NEXT:    sub a6, a3, a2
 ; RV64IA-NEXT:    addi a4, zero, 255
 ; RV64IA-NEXT:    sllw a7, a4, a2
 ; RV64IA-NEXT:    slli a1, a1, 56
 ; RV64IA-NEXT:    srai a1, a1, 56
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB35_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w a5, (a0)
 ; RV64IA-NEXT:    and a4, a5, a7
 ; RV64IA-NEXT:    mv a3, a5
 ; RV64IA-NEXT:    sll a4, a4, a6
 ; RV64IA-NEXT:    sra a4, a4, a6
 ; RV64IA-NEXT:    bge a4, a1, .LBB35_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB35_1 Depth=1
 ; RV64IA-NEXT:    xor a3, a5, a1
 ; RV64IA-NEXT:    and a3, a3, a7
 ; RV64IA-NEXT:    xor a3, a5, a3
 ; RV64IA-NEXT:  .LBB35_3: # in Loop: Header=BB35_1 Depth=1
 ; RV64IA-NEXT:    sc.w a3, a3, (a0)
 ; RV64IA-NEXT:    bnez a3, .LBB35_1
 ; RV64IA-NEXT:  # %bb.4:
 ; RV64IA-NEXT:    srlw a0, a5, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw max i8* %a, i8 %b monotonic
   ret i8 %1
 }

 define i8 @atomicrmw_max_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_max_i8_acquire:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
 ; RV32I-NEXT:    sw s1, 24(sp)
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 24
 ; RV32I-NEXT:    srai s1, a1, 24
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB36_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 24
 ; RV32I-NEXT:    srai a1, a1, 24
 ; RV32I-NEXT:    mv a2, a0
 ; RV32I-NEXT:    blt s1, a1, .LBB36_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB36_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB36_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB36_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
 ; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 2
 ; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_1
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB36_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
 ; RV32I-NEXT:    lw s1, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_max_i8_acquire:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 24
 ; RV32IA-NEXT:    sub a6, a3, a2
 ; RV32IA-NEXT:    addi a4, zero, 255
 ; RV32IA-NEXT:    sll a7, a4, a2
 ; RV32IA-NEXT:    slli a1, a1, 24
 ; RV32IA-NEXT:    srai a1, a1, 24
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB36_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w.aq a5, (a0)
 ; RV32IA-NEXT:    and a4, a5, a7
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    sll a4, a4, a6
 ; RV32IA-NEXT:    sra a4, a4, a6
 ; RV32IA-NEXT:    bge a4, a1, .LBB36_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB36_1 Depth=1
 ; RV32IA-NEXT:    xor a3, a5, a1
 ; RV32IA-NEXT:    and a3, a3, a7
 ; RV32IA-NEXT:    xor a3, a5, a3
 ; RV32IA-NEXT:  .LBB36_3: # in Loop: Header=BB36_1 Depth=1
 ; RV32IA-NEXT:    sc.w a3, a3, (a0)
 ; RV32IA-NEXT:    bnez a3, .LBB36_1
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_max_i8_acquire:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s1, 32(sp)
 ; RV64I-NEXT:    sd s2, 24(sp)
 ; RV64I-NEXT:    sd s3, 16(sp)
 ; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 56
 ; RV64I-NEXT:    srai s1, a1, 56
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB36_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 56
 ; RV64I-NEXT:    srai a1, a1, 56
 ; RV64I-NEXT:    mv a2, a0
 ; RV64I-NEXT:    blt s1, a1, .LBB36_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB36_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB36_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB36_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 2
 ; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_1
 ; RV64I-NEXT:    mv a1, a0
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB36_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    ld s4, 8(sp)
 ; RV64I-NEXT:    ld s3, 16(sp)
 ; RV64I-NEXT:    ld s2, 24(sp)
 ; RV64I-NEXT:    ld s1, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_max_i8_acquire:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 56
 ; RV64IA-NEXT:    sub a6, a3, a2
 ; RV64IA-NEXT:    addi a4, zero, 255
 ; RV64IA-NEXT:    sllw a7, a4, a2
 ; RV64IA-NEXT:    slli a1, a1, 56
 ; RV64IA-NEXT:    srai a1, a1, 56
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB36_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w.aq a5, (a0)
 ; RV64IA-NEXT:    and a4, a5, a7
 ; RV64IA-NEXT:    mv a3, a5
 ; RV64IA-NEXT:    sll a4, a4, a6
 ; RV64IA-NEXT:    sra a4, a4, a6
 ; RV64IA-NEXT:    bge a4, a1, .LBB36_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB36_1 Depth=1
 ; RV64IA-NEXT:    xor a3, a5, a1
 ; RV64IA-NEXT:    and a3, a3, a7
 ; RV64IA-NEXT:    xor a3, a5, a3
 ; RV64IA-NEXT:  .LBB36_3: # in Loop: Header=BB36_1 Depth=1
 ; RV64IA-NEXT:    sc.w a3, a3, (a0)
 ; RV64IA-NEXT:    bnez a3, .LBB36_1
 ; RV64IA-NEXT:  # %bb.4:
 ; RV64IA-NEXT:    srlw a0, a5, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw max i8* %a, i8 %b acquire
   ret i8 %1
 }

 define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_max_i8_release:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
 ; RV32I-NEXT:    sw s1, 24(sp)
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 24
 ; RV32I-NEXT:    srai s1, a1, 24
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB37_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 24
 ; RV32I-NEXT:    srai a1, a1, 24
 ; RV32I-NEXT:    mv a2, a0
 ; RV32I-NEXT:    blt s1, a1, .LBB37_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB37_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB37_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB37_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
 ; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 3
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_1
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB37_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
 ; RV32I-NEXT:    lw s1, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_max_i8_release:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 24
 ; RV32IA-NEXT:    sub a6, a3, a2
 ; RV32IA-NEXT:    addi a4, zero, 255
 ; RV32IA-NEXT:    sll a7, a4, a2
 ; RV32IA-NEXT:    slli a1, a1, 24
 ; RV32IA-NEXT:    srai a1, a1, 24
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB37_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w a5, (a0)
 ; RV32IA-NEXT:    and a4, a5, a7
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    sll a4, a4, a6
 ; RV32IA-NEXT:    sra a4, a4, a6
 ; RV32IA-NEXT:    bge a4, a1, .LBB37_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB37_1 Depth=1
 ; RV32IA-NEXT:    xor a3, a5, a1
 ; RV32IA-NEXT:    and a3, a3, a7
 ; RV32IA-NEXT:    xor a3, a5, a3
 ; RV32IA-NEXT:  .LBB37_3: # in Loop: Header=BB37_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a3, a3, (a0)
 ; RV32IA-NEXT:    bnez a3, .LBB37_1
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_max_i8_release:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s1, 32(sp)
 ; RV64I-NEXT:    sd s2, 24(sp)
 ; RV64I-NEXT:    sd s3, 16(sp)
 ; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 56
 ; RV64I-NEXT:    srai s1, a1, 56
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB37_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 56
 ; RV64I-NEXT:    srai a1, a1, 56
 ; RV64I-NEXT:    mv a2, a0
 ; RV64I-NEXT:    blt s1, a1, .LBB37_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB37_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB37_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB37_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    call __atomic_compare_exchange_1
 ; RV64I-NEXT:    mv a1, a0
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB37_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    ld s4, 8(sp)
 ; RV64I-NEXT:    ld s3, 16(sp)
 ; RV64I-NEXT:    ld s2, 24(sp)
 ; RV64I-NEXT:    ld s1, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_max_i8_release:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 56
 ; RV64IA-NEXT:    sub a6, a3, a2
 ; RV64IA-NEXT:    addi a4, zero, 255
 ; RV64IA-NEXT:    sllw a7, a4, a2
 ; RV64IA-NEXT:    slli a1, a1, 56
 ; RV64IA-NEXT:    srai a1, a1, 56
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB37_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w a5, (a0)
 ; RV64IA-NEXT:    and a4, a5, a7
 ; RV64IA-NEXT:    mv a3, a5
 ; RV64IA-NEXT:    sll a4, a4, a6
 ; RV64IA-NEXT:    sra a4, a4, a6
 ; RV64IA-NEXT:    bge a4, a1, .LBB37_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB37_1 Depth=1
 ; RV64IA-NEXT:    xor a3, a5, a1
 ; RV64IA-NEXT:    and a3, a3, a7
 ; RV64IA-NEXT:    xor a3, a5, a3
 ; RV64IA-NEXT:  .LBB37_3: # in Loop: Header=BB37_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a3, a3, (a0)
 ; RV64IA-NEXT:    bnez a3, .LBB37_1
 ; RV64IA-NEXT:  # %bb.4:
 ; RV64IA-NEXT:    srlw a0, a5, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw max i8* %a, i8 %b release
   ret i8 %1
 }

 define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_max_i8_acq_rel:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
 ; RV32I-NEXT:    sw s1, 24(sp)
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 24
 ; RV32I-NEXT:    srai s1, a1, 24
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB38_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 24
 ; RV32I-NEXT:    srai a1, a1, 24
 ; RV32I-NEXT:    mv a2, a0
 ; RV32I-NEXT:    blt s1, a1, .LBB38_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB38_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB38_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB38_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
 ; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 4
 ; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_1
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB38_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
 ; RV32I-NEXT:    lw s1, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_max_i8_acq_rel:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 24
 ; RV32IA-NEXT:    sub a6, a3, a2
 ; RV32IA-NEXT:    addi a4, zero, 255
 ; RV32IA-NEXT:    sll a7, a4, a2
 ; RV32IA-NEXT:    slli a1, a1, 24
 ; RV32IA-NEXT:    srai a1, a1, 24
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB38_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w.aq a5, (a0)
 ; RV32IA-NEXT:    and a4, a5, a7
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    sll a4, a4, a6
 ; RV32IA-NEXT:    sra a4, a4, a6
 ; RV32IA-NEXT:    bge a4, a1, .LBB38_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB38_1 Depth=1
 ; RV32IA-NEXT:    xor a3, a5, a1
 ; RV32IA-NEXT:    and a3, a3, a7
 ; RV32IA-NEXT:    xor a3, a5, a3
 ; RV32IA-NEXT:  .LBB38_3: # in Loop: Header=BB38_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a3, a3, (a0)
 ; RV32IA-NEXT:    bnez a3, .LBB38_1
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_max_i8_acq_rel:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s1, 32(sp)
 ; RV64I-NEXT:    sd s2, 24(sp)
 ; RV64I-NEXT:    sd s3, 16(sp)
 ; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 56
 ; RV64I-NEXT:    srai s1, a1, 56
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB38_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 56
 ; RV64I-NEXT:    srai a1, a1, 56
 ; RV64I-NEXT:    mv a2, a0
 ; RV64I-NEXT:    blt s1, a1, .LBB38_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB38_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB38_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB38_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 4
 ; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_1
 ; RV64I-NEXT:    mv a1, a0
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB38_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    ld s4, 8(sp)
 ; RV64I-NEXT:    ld s3, 16(sp)
 ; RV64I-NEXT:    ld s2, 24(sp)
 ; RV64I-NEXT:    ld s1, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_max_i8_acq_rel:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 56
 ; RV64IA-NEXT:    sub a6, a3, a2
 ; RV64IA-NEXT:    addi a4, zero, 255
 ; RV64IA-NEXT:    sllw a7, a4, a2
 ; RV64IA-NEXT:    slli a1, a1, 56
 ; RV64IA-NEXT:    srai a1, a1, 56
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB38_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w.aq a5, (a0)
 ; RV64IA-NEXT:    and a4, a5, a7
 ; RV64IA-NEXT:    mv a3, a5
 ; RV64IA-NEXT:    sll a4, a4, a6
 ; RV64IA-NEXT:    sra a4, a4, a6
 ; RV64IA-NEXT:    bge a4, a1, .LBB38_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB38_1 Depth=1
 ; RV64IA-NEXT:    xor a3, a5, a1
 ; RV64IA-NEXT:    and a3, a3, a7
 ; RV64IA-NEXT:    xor a3, a5, a3
 ; RV64IA-NEXT:  .LBB38_3: # in Loop: Header=BB38_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a3, a3, (a0)
 ; RV64IA-NEXT:    bnez a3, .LBB38_1
 ; RV64IA-NEXT:  # %bb.4:
 ; RV64IA-NEXT:    srlw a0, a5, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw max i8* %a, i8 %b acq_rel
   ret i8 %1
 }

 define i8 @atomicrmw_max_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_max_i8_seq_cst:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
 ; RV32I-NEXT:    sw s1, 24(sp)
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 24
 ; RV32I-NEXT:    srai s1, a1, 24
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB39_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 24
 ; RV32I-NEXT:    srai a1, a1, 24
 ; RV32I-NEXT:    mv a2, a0
 ; RV32I-NEXT:    blt s1, a1, .LBB39_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB39_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB39_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB39_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
 ; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 5
 ; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_1
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB39_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
 ; RV32I-NEXT:    lw s1, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_max_i8_seq_cst:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 24
 ; RV32IA-NEXT:    sub a6, a3, a2
 ; RV32IA-NEXT:    addi a4, zero, 255
 ; RV32IA-NEXT:    sll a7, a4, a2
 ; RV32IA-NEXT:    slli a1, a1, 24
 ; RV32IA-NEXT:    srai a1, a1, 24
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB39_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w.aqrl a5, (a0)
 ; RV32IA-NEXT:    and a4, a5, a7
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    sll a4, a4, a6
 ; RV32IA-NEXT:    sra a4, a4, a6
 ; RV32IA-NEXT:    bge a4, a1, .LBB39_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB39_1 Depth=1
 ; RV32IA-NEXT:    xor a3, a5, a1
 ; RV32IA-NEXT:    and a3, a3, a7
 ; RV32IA-NEXT:    xor a3, a5, a3
 ; RV32IA-NEXT:  .LBB39_3: # in Loop: Header=BB39_1 Depth=1
 ; RV32IA-NEXT:    sc.w.aqrl a3, a3, (a0)
 ; RV32IA-NEXT:    bnez a3, .LBB39_1
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_max_i8_seq_cst:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s1, 32(sp)
 ; RV64I-NEXT:    sd s2, 24(sp)
 ; RV64I-NEXT:    sd s3, 16(sp)
 ; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 56
 ; RV64I-NEXT:    srai s1, a1, 56
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB39_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 56
 ; RV64I-NEXT:    srai a1, a1, 56
 ; RV64I-NEXT:    mv a2, a0
 ; RV64I-NEXT:    blt s1, a1, .LBB39_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB39_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB39_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB39_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 5
 ; RV64I-NEXT:    addi a4, zero, 5
 ; RV64I-NEXT:    call __atomic_compare_exchange_1
 ; RV64I-NEXT:    mv a1, a0
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB39_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    ld s4, 8(sp)
 ; RV64I-NEXT:    ld s3, 16(sp)
 ; RV64I-NEXT:    ld s2, 24(sp)
 ; RV64I-NEXT:    ld s1, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_max_i8_seq_cst:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 56
 ; RV64IA-NEXT:    sub a6, a3, a2
 ; RV64IA-NEXT:    addi a4, zero, 255
 ; RV64IA-NEXT:    sllw a7, a4, a2
 ; RV64IA-NEXT:    slli a1, a1, 56
 ; RV64IA-NEXT:    srai a1, a1, 56
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB39_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w.aqrl a5, (a0)
 ; RV64IA-NEXT:    and a4, a5, a7
 ; RV64IA-NEXT:    mv a3, a5
 ; RV64IA-NEXT:    sll a4, a4, a6
 ; RV64IA-NEXT:    sra a4, a4, a6
 ; RV64IA-NEXT:    bge a4, a1, .LBB39_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB39_1 Depth=1
 ; RV64IA-NEXT:    xor a3, a5, a1
 ; RV64IA-NEXT:    and a3, a3, a7
 ; RV64IA-NEXT:    xor a3, a5, a3
 ; RV64IA-NEXT:  .LBB39_3: # in Loop: Header=BB39_1 Depth=1
 ; RV64IA-NEXT:    sc.w.aqrl a3, a3, (a0)
 ; RV64IA-NEXT:    bnez a3, .LBB39_1
 ; RV64IA-NEXT:  # %bb.4:
 ; RV64IA-NEXT:    srlw a0, a5, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw max i8* %a, i8 %b seq_cst
   ret i8 %1
 }

 define i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_min_i8_monotonic:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
 ; RV32I-NEXT:    sw s1, 24(sp)
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 24
 ; RV32I-NEXT:    srai s1, a1, 24
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB40_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 24
 ; RV32I-NEXT:    srai a1, a1, 24
 ; RV32I-NEXT:    mv a2, a0
 ; RV32I-NEXT:    bge s1, a1, .LBB40_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB40_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB40_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB40_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
 ; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    mv a3, zero
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_1
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB40_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
 ; RV32I-NEXT:    lw s1, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_min_i8_monotonic:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 24
 ; RV32IA-NEXT:    sub a6, a3, a2
 ; RV32IA-NEXT:    addi a4, zero, 255
 ; RV32IA-NEXT:    sll a7, a4, a2
 ; RV32IA-NEXT:    slli a1, a1, 24
 ; RV32IA-NEXT:    srai a1, a1, 24
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB40_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w a5, (a0)
 ; RV32IA-NEXT:    and a4, a5, a7
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    sll a4, a4, a6
 ; RV32IA-NEXT:    sra a4, a4, a6
 ; RV32IA-NEXT:    bge a1, a4, .LBB40_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB40_1 Depth=1
 ; RV32IA-NEXT:    xor a3, a5, a1
 ; RV32IA-NEXT:    and a3, a3, a7
 ; RV32IA-NEXT:    xor a3, a5, a3
 ; RV32IA-NEXT:  .LBB40_3: # in Loop: Header=BB40_1 Depth=1
 ; RV32IA-NEXT:    sc.w a3, a3, (a0)
 ; RV32IA-NEXT:    bnez a3, .LBB40_1
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_min_i8_monotonic:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s1, 32(sp)
 ; RV64I-NEXT:    sd s2, 24(sp)
 ; RV64I-NEXT:    sd s3, 16(sp)
 ; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 56
 ; RV64I-NEXT:    srai s1, a1, 56
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB40_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 56
 ; RV64I-NEXT:    srai a1, a1, 56
 ; RV64I-NEXT:    mv a2, a0
 ; RV64I-NEXT:    bge s1, a1, .LBB40_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB40_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB40_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB40_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    mv a3, zero
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    call __atomic_compare_exchange_1
 ; RV64I-NEXT:    mv a1, a0
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB40_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    ld s4, 8(sp)
 ; RV64I-NEXT:    ld s3, 16(sp)
 ; RV64I-NEXT:    ld s2, 24(sp)
 ; RV64I-NEXT:    ld s1, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_min_i8_monotonic:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 56
 ; RV64IA-NEXT:    sub a6, a3, a2
 ; RV64IA-NEXT:    addi a4, zero, 255
 ; RV64IA-NEXT:    sllw a7, a4, a2
 ; RV64IA-NEXT:    slli a1, a1, 56
 ; RV64IA-NEXT:    srai a1, a1, 56
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB40_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w a5, (a0)
 ; RV64IA-NEXT:    and a4, a5, a7
 ; RV64IA-NEXT:    mv a3, a5
 ; RV64IA-NEXT:    sll a4, a4, a6
 ; RV64IA-NEXT:    sra a4, a4, a6
 ; RV64IA-NEXT:    bge a1, a4, .LBB40_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB40_1 Depth=1
 ; RV64IA-NEXT:    xor a3, a5, a1
 ; RV64IA-NEXT:    and a3, a3, a7
 ; RV64IA-NEXT:    xor a3, a5, a3
 ; RV64IA-NEXT:  .LBB40_3: # in Loop: Header=BB40_1 Depth=1
 ; RV64IA-NEXT:    sc.w a3, a3, (a0)
 ; RV64IA-NEXT:    bnez a3, .LBB40_1
 ; RV64IA-NEXT:  # %bb.4:
 ; RV64IA-NEXT:    srlw a0, a5, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw min i8* %a, i8 %b monotonic
   ret i8 %1
 }

 define i8 @atomicrmw_min_i8_acquire(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_min_i8_acquire:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
 ; RV32I-NEXT:    sw s1, 24(sp)
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 24
 ; RV32I-NEXT:    srai s1, a1, 24
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB41_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 24
 ; RV32I-NEXT:    srai a1, a1, 24
 ; RV32I-NEXT:    mv a2, a0
 ; RV32I-NEXT:    bge s1, a1, .LBB41_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB41_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB41_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB41_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
 ; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 2
 ; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_1
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB41_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
 ; RV32I-NEXT:    lw s1, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_min_i8_acquire:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 24
 ; RV32IA-NEXT:    sub a6, a3, a2
 ; RV32IA-NEXT:    addi a4, zero, 255
 ; RV32IA-NEXT:    sll a7, a4, a2
 ; RV32IA-NEXT:    slli a1, a1, 24
 ; RV32IA-NEXT:    srai a1, a1, 24
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB41_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w.aq a5, (a0)
 ; RV32IA-NEXT:    and a4, a5, a7
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    sll a4, a4, a6
 ; RV32IA-NEXT:    sra a4, a4, a6
 ; RV32IA-NEXT:    bge a1, a4, .LBB41_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB41_1 Depth=1
 ; RV32IA-NEXT:    xor a3, a5, a1
 ; RV32IA-NEXT:    and a3, a3, a7
 ; RV32IA-NEXT:    xor a3, a5, a3
 ; RV32IA-NEXT:  .LBB41_3: # in Loop: Header=BB41_1 Depth=1
 ; RV32IA-NEXT:    sc.w a3, a3, (a0)
 ; RV32IA-NEXT:    bnez a3, .LBB41_1
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_min_i8_acquire:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s1, 32(sp)
 ; RV64I-NEXT:    sd s2, 24(sp)
 ; RV64I-NEXT:    sd s3, 16(sp)
 ; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 56
 ; RV64I-NEXT:    srai s1, a1, 56
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB41_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 56
 ; RV64I-NEXT:    srai a1, a1, 56
 ; RV64I-NEXT:    mv a2, a0
 ; RV64I-NEXT:    bge s1, a1, .LBB41_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB41_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB41_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB41_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 2
 ; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_1
 ; RV64I-NEXT:    mv a1, a0
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB41_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    ld s4, 8(sp)
 ; RV64I-NEXT:    ld s3, 16(sp)
 ; RV64I-NEXT:    ld s2, 24(sp)
 ; RV64I-NEXT:    ld s1, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_min_i8_acquire:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 56
 ; RV64IA-NEXT:    sub a6, a3, a2
 ; RV64IA-NEXT:    addi a4, zero, 255
 ; RV64IA-NEXT:    sllw a7, a4, a2
 ; RV64IA-NEXT:    slli a1, a1, 56
 ; RV64IA-NEXT:    srai a1, a1, 56
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB41_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w.aq a5, (a0)
 ; RV64IA-NEXT:    and a4, a5, a7
 ; RV64IA-NEXT:    mv a3, a5
 ; RV64IA-NEXT:    sll a4, a4, a6
 ; RV64IA-NEXT:    sra a4, a4, a6
 ; RV64IA-NEXT:    bge a1, a4, .LBB41_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB41_1 Depth=1
 ; RV64IA-NEXT:    xor a3, a5, a1
 ; RV64IA-NEXT:    and a3, a3, a7
 ; RV64IA-NEXT:    xor a3, a5, a3
 ; RV64IA-NEXT:  .LBB41_3: # in Loop: Header=BB41_1 Depth=1
 ; RV64IA-NEXT:    sc.w a3, a3, (a0)
 ; RV64IA-NEXT:    bnez a3, .LBB41_1
 ; RV64IA-NEXT:  # %bb.4:
 ; RV64IA-NEXT:    srlw a0, a5, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw min i8* %a, i8 %b acquire
   ret i8 %1
 }

 define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_min_i8_release:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
 ; RV32I-NEXT:    sw s1, 24(sp)
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 24
 ; RV32I-NEXT:    srai s1, a1, 24
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB42_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 24
 ; RV32I-NEXT:    srai a1, a1, 24
 ; RV32I-NEXT:    mv a2, a0
 ; RV32I-NEXT:    bge s1, a1, .LBB42_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB42_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB42_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB42_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
 ; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 3
 ; RV32I-NEXT:    mv a4, zero
 ; RV32I-NEXT:    call __atomic_compare_exchange_1
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB42_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
 ; RV32I-NEXT:    lw s1, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_min_i8_release:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 24
 ; RV32IA-NEXT:    sub a6, a3, a2
 ; RV32IA-NEXT:    addi a4, zero, 255
 ; RV32IA-NEXT:    sll a7, a4, a2
 ; RV32IA-NEXT:    slli a1, a1, 24
 ; RV32IA-NEXT:    srai a1, a1, 24
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB42_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w a5, (a0)
 ; RV32IA-NEXT:    and a4, a5, a7
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    sll a4, a4, a6
 ; RV32IA-NEXT:    sra a4, a4, a6
 ; RV32IA-NEXT:    bge a1, a4, .LBB42_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB42_1 Depth=1
 ; RV32IA-NEXT:    xor a3, a5, a1
 ; RV32IA-NEXT:    and a3, a3, a7
 ; RV32IA-NEXT:    xor a3, a5, a3
 ; RV32IA-NEXT:  .LBB42_3: # in Loop: Header=BB42_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a3, a3, (a0)
 ; RV32IA-NEXT:    bnez a3, .LBB42_1
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_min_i8_release:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s1, 32(sp)
 ; RV64I-NEXT:    sd s2, 24(sp)
 ; RV64I-NEXT:    sd s3, 16(sp)
 ; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 56
 ; RV64I-NEXT:    srai s1, a1, 56
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB42_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 56
 ; RV64I-NEXT:    srai a1, a1, 56
 ; RV64I-NEXT:    mv a2, a0
 ; RV64I-NEXT:    bge s1, a1, .LBB42_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB42_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB42_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB42_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 3
 ; RV64I-NEXT:    mv a4, zero
 ; RV64I-NEXT:    call __atomic_compare_exchange_1
 ; RV64I-NEXT:    mv a1, a0
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB42_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    ld s4, 8(sp)
 ; RV64I-NEXT:    ld s3, 16(sp)
 ; RV64I-NEXT:    ld s2, 24(sp)
 ; RV64I-NEXT:    ld s1, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_min_i8_release:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 56
 ; RV64IA-NEXT:    sub a6, a3, a2
 ; RV64IA-NEXT:    addi a4, zero, 255
 ; RV64IA-NEXT:    sllw a7, a4, a2
 ; RV64IA-NEXT:    slli a1, a1, 56
 ; RV64IA-NEXT:    srai a1, a1, 56
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB42_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w a5, (a0)
 ; RV64IA-NEXT:    and a4, a5, a7
 ; RV64IA-NEXT:    mv a3, a5
 ; RV64IA-NEXT:    sll a4, a4, a6
 ; RV64IA-NEXT:    sra a4, a4, a6
 ; RV64IA-NEXT:    bge a1, a4, .LBB42_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB42_1 Depth=1
 ; RV64IA-NEXT:    xor a3, a5, a1
 ; RV64IA-NEXT:    and a3, a3, a7
 ; RV64IA-NEXT:    xor a3, a5, a3
 ; RV64IA-NEXT:  .LBB42_3: # in Loop: Header=BB42_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a3, a3, (a0)
 ; RV64IA-NEXT:    bnez a3, .LBB42_1
 ; RV64IA-NEXT:  # %bb.4:
 ; RV64IA-NEXT:    srlw a0, a5, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw min i8* %a, i8 %b release
   ret i8 %1
 }

 define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_min_i8_acq_rel:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
 ; RV32I-NEXT:    sw s1, 24(sp)
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 24
 ; RV32I-NEXT:    srai s1, a1, 24
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB43_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 24
 ; RV32I-NEXT:    srai a1, a1, 24
 ; RV32I-NEXT:    mv a2, a0
 ; RV32I-NEXT:    bge s1, a1, .LBB43_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB43_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB43_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB43_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
 ; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 4
 ; RV32I-NEXT:    addi a4, zero, 2
 ; RV32I-NEXT:    call __atomic_compare_exchange_1
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB43_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
 ; RV32I-NEXT:    lw s1, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_min_i8_acq_rel:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 24
 ; RV32IA-NEXT:    sub a6, a3, a2
 ; RV32IA-NEXT:    addi a4, zero, 255
 ; RV32IA-NEXT:    sll a7, a4, a2
 ; RV32IA-NEXT:    slli a1, a1, 24
 ; RV32IA-NEXT:    srai a1, a1, 24
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB43_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w.aq a5, (a0)
 ; RV32IA-NEXT:    and a4, a5, a7
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    sll a4, a4, a6
 ; RV32IA-NEXT:    sra a4, a4, a6
 ; RV32IA-NEXT:    bge a1, a4, .LBB43_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB43_1 Depth=1
 ; RV32IA-NEXT:    xor a3, a5, a1
 ; RV32IA-NEXT:    and a3, a3, a7
 ; RV32IA-NEXT:    xor a3, a5, a3
 ; RV32IA-NEXT:  .LBB43_3: # in Loop: Header=BB43_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a3, a3, (a0)
 ; RV32IA-NEXT:    bnez a3, .LBB43_1
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_min_i8_acq_rel:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s1, 32(sp)
 ; RV64I-NEXT:    sd s2, 24(sp)
 ; RV64I-NEXT:    sd s3, 16(sp)
 ; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 56
 ; RV64I-NEXT:    srai s1, a1, 56
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB43_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 56
 ; RV64I-NEXT:    srai a1, a1, 56
 ; RV64I-NEXT:    mv a2, a0
 ; RV64I-NEXT:    bge s1, a1, .LBB43_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB43_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB43_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB43_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 4
 ; RV64I-NEXT:    addi a4, zero, 2
 ; RV64I-NEXT:    call __atomic_compare_exchange_1
 ; RV64I-NEXT:    mv a1, a0
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB43_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    ld s4, 8(sp)
 ; RV64I-NEXT:    ld s3, 16(sp)
 ; RV64I-NEXT:    ld s2, 24(sp)
 ; RV64I-NEXT:    ld s1, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_min_i8_acq_rel:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 56
 ; RV64IA-NEXT:    sub a6, a3, a2
 ; RV64IA-NEXT:    addi a4, zero, 255
 ; RV64IA-NEXT:    sllw a7, a4, a2
 ; RV64IA-NEXT:    slli a1, a1, 56
 ; RV64IA-NEXT:    srai a1, a1, 56
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB43_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w.aq a5, (a0)
 ; RV64IA-NEXT:    and a4, a5, a7
 ; RV64IA-NEXT:    mv a3, a5
 ; RV64IA-NEXT:    sll a4, a4, a6
 ; RV64IA-NEXT:    sra a4, a4, a6
 ; RV64IA-NEXT:    bge a1, a4, .LBB43_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB43_1 Depth=1
 ; RV64IA-NEXT:    xor a3, a5, a1
 ; RV64IA-NEXT:    and a3, a3, a7
 ; RV64IA-NEXT:    xor a3, a5, a3
 ; RV64IA-NEXT:  .LBB43_3: # in Loop: Header=BB43_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a3, a3, (a0)
 ; RV64IA-NEXT:    bnez a3, .LBB43_1
 ; RV64IA-NEXT:  # %bb.4:
 ; RV64IA-NEXT:    srlw a0, a5, a2
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw min i8* %a, i8 %b acq_rel
   ret i8 %1
 }

 define i8 @atomicrmw_min_i8_seq_cst(i8 *%a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_min_i8_seq_cst:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp)
 ; RV32I-NEXT:    sw s1, 24(sp)
 ; RV32I-NEXT:    sw s2, 20(sp)
 ; RV32I-NEXT:    sw s3, 16(sp)
 ; RV32I-NEXT:    sw s4, 12(sp)
 ; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
 ; RV32I-NEXT:    slli a1, a1, 24
 ; RV32I-NEXT:    srai s1, a1, 24
 ; RV32I-NEXT:    addi s3, sp, 11
 ; RV32I-NEXT:  .LBB44_1: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    slli a1, a0, 24
 ; RV32I-NEXT:    srai a1, a1, 24
 ; RV32I-NEXT:    mv a2, a0
 ; RV32I-NEXT:    bge s1, a1, .LBB44_3
 ; RV32I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB44_1 Depth=1
 ; RV32I-NEXT:    mv a2, s2
 ; RV32I-NEXT:  .LBB44_3: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB44_1 Depth=1
 ; RV32I-NEXT:    sb a0, 11(sp)
 ; RV32I-NEXT:    mv a0, s4
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    addi a3, zero, 5
 ; RV32I-NEXT:    addi a4, zero, 5
 ; RV32I-NEXT:    call __atomic_compare_exchange_1
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    lb a0, 11(sp)
 ; RV32I-NEXT:    beqz a1, .LBB44_1
 ; RV32I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV32I-NEXT:    lw s4, 12(sp)
 ; RV32I-NEXT:    lw s3, 16(sp)
 ; RV32I-NEXT:    lw s2, 20(sp)
 ; RV32I-NEXT:    lw s1, 24(sp)
 ; RV32I-NEXT:    lw ra, 28(sp)
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV32IA-LABEL: atomicrmw_min_i8_seq_cst:
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    slli a2, a0, 3
 ; RV32IA-NEXT:    andi a2, a2, 24
 ; RV32IA-NEXT:    addi a3, zero, 24
 ; RV32IA-NEXT:    sub a6, a3, a2
 ; RV32IA-NEXT:    addi a4, zero, 255
 ; RV32IA-NEXT:    sll a7, a4, a2
 ; RV32IA-NEXT:    slli a1, a1, 24
 ; RV32IA-NEXT:    srai a1, a1, 24
 ; RV32IA-NEXT:    sll a1, a1, a2
 ; RV32IA-NEXT:    andi a0, a0, -4
 ; RV32IA-NEXT:  .LBB44_1: # =>This Inner Loop Header: Depth=1
 ; RV32IA-NEXT:    lr.w.aqrl a5, (a0)
 ; RV32IA-NEXT:    and a4, a5, a7
 ; RV32IA-NEXT:    mv a3, a5
 ; RV32IA-NEXT:    sll a4, a4, a6
 ; RV32IA-NEXT:    sra a4, a4, a6
 ; RV32IA-NEXT:    bge a1, a4, .LBB44_3
 ; RV32IA-NEXT:  # %bb.2: # in Loop: Header=BB44_1 Depth=1
 ; RV32IA-NEXT:    xor a3, a5, a1
 ; RV32IA-NEXT:    and a3, a3, a7
 ; RV32IA-NEXT:    xor a3, a5, a3
 ; RV32IA-NEXT:  .LBB44_3: # in Loop: Header=BB44_1 Depth=1
 ; RV32IA-NEXT:    sc.w.aqrl a3, a3, (a0)
 ; RV32IA-NEXT:    bnez a3, .LBB44_1
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
 ;
 ; RV64I-LABEL: atomicrmw_min_i8_seq_cst:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp)
 ; RV64I-NEXT:    sd s1, 32(sp)
 ; RV64I-NEXT:    sd s2, 24(sp)
 ; RV64I-NEXT:    sd s3, 16(sp)
 ; RV64I-NEXT:    sd s4, 8(sp)
 ; RV64I-NEXT:    mv s2, a1
 ; RV64I-NEXT:    mv s4, a0
 ; RV64I-NEXT:    lbu a0, 0(a0)
 ; RV64I-NEXT:    slli a1, a1, 56
 ; RV64I-NEXT:    srai s1, a1, 56
 ; RV64I-NEXT:    addi s3, sp, 7
 ; RV64I-NEXT:  .LBB44_1: # %atomicrmw.start
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    slli a1, a0, 56
 ; RV64I-NEXT:    srai a1, a1, 56
 ; RV64I-NEXT:    mv a2, a0
 ; RV64I-NEXT:    bge s1, a1, .LBB44_3
 ; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB44_1 Depth=1
 ; RV64I-NEXT:    mv a2, s2
 ; RV64I-NEXT:  .LBB44_3: # %atomicrmw.start
 ; RV64I-NEXT:    # in Loop: Header=BB44_1 Depth=1
 ; RV64I-NEXT:    sb a0, 7(sp)
 ; RV64I-NEXT:    mv a0, s4
 ; RV64I-NEXT:    mv a1, s3
 ; RV64I-NEXT:    addi a3, zero, 5
 ; RV64I-NEXT:    addi a4, zero, 5
 ; RV64I-NEXT:    call __atomic_compare_exchange_1
 ; RV64I-NEXT:    mv a1, a0
 ; RV64I-NEXT:    lb a0, 7(sp)
 ; RV64I-NEXT:    beqz a1, .LBB44_1
 ; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
 ; RV64I-NEXT:    ld s4, 8(sp)
 ; RV64I-NEXT:    ld s3, 16(sp)
 ; RV64I-NEXT:    ld s2, 24(sp)
 ; RV64I-NEXT:    ld s1, 32(sp)
 ; RV64I-NEXT:    ld ra, 40(sp)
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 ;
 ; RV64IA-LABEL: atomicrmw_min_i8_seq_cst:
 ; RV64IA:       # %bb.0:
 ; RV64IA-NEXT:    slli a2, a0, 3
 ; RV64IA-NEXT:    andi a2, a2, 24
 ; RV64IA-NEXT:    addi a3, zero, 56
 ; RV64IA-NEXT:    sub a6, a3, a2
 ; RV64IA-NEXT:    addi a4, zero, 255
 ; RV64IA-NEXT:    sllw a7, a4, a2
 ; RV64IA-NEXT:    slli a1, a1, 56
 ; RV64IA-NEXT:    srai a1, a1, 56
 ; RV64IA-NEXT:    sllw a1, a1, a2
 ; RV64IA-NEXT:    andi a0, a0, -4
 ; RV64IA-NEXT:  .LBB44_1: # =>This Inner Loop Header: Depth=1
 ; RV64IA-NEXT:    lr.w.aqrl a5, (a0)
 ; RV64IA-NEXT:    and a4, a5, a7
 ; RV64IA-NEXT:    mv a3, a5
 ; RV64IA-NEXT:    sll a4, a4, a6
 ; RV64IA-NEXT:    sra a4, a4, a6
 ; RV64IA-NEXT:    bge a1, a4, .LBB44_3
 ; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB44_1 Depth=1
 ; RV64IA-NEXT:    xor a3, a5, a1
 ; RV64IA-NEXT:    and a3, a3, a7
 ; RV64IA-NEXT:    xor a3, a5, a3
 ; RV64IA-NEXT:  .LBB44_3: # in Loop: Header=BB44_1 Depth=1
 ; RV64IA-NEXT:    sc.w.aqrl a3, a3, (a0)
 ; RV64IA-NEXT:    bnez a3, .LBB44_1