commit 00d07572968ab6e3611744ca0d700e40456c0eec
author Matt Arsenault <Matthew.Arsenault@amd.com> Tue Feb 19 16:10:16 2019 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Tue Feb 19 16:10:16 2019 +0000
tree 6c04f098b4bd364b54353bd768816c0a56093b6f
parent cd7aa81b8b2a2e7f74875799d33188d94dd053c4

GlobalISel: Verify g_insert

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354342 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/MachineVerifier.cpp

diff --git a/lib/CodeGen/MachineVerifier.cpp b/lib/CodeGen/MachineVerifier.cpp
index 99cbe6e..4d38870 100644
--- a/lib/CodeGen/MachineVerifier.cpp
+++ b/lib/CodeGen/MachineVerifier.cpp
@@ -1288,6 +1288,30 @@
       report("extract reads past end of register", MI);
     break;
   }
+  case TargetOpcode::G_INSERT: {
+    const MachineOperand &SrcOp = MI->getOperand(2);
+    if (!SrcOp.isReg()) {
+      report("insert source must be a register", MI);
+      break;
+    }
+
+    const MachineOperand &OffsetOp = MI->getOperand(3);
+    if (!OffsetOp.isImm()) {
+      report("insert offset must be a constant", MI);
+      break;
+    }
+
+    unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
+    unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
+
+    if (DstSize <= SrcSize)
+      report("inserted size must be smaller than total register", MI);
+
+    if (SrcSize + OffsetOp.getImm() > DstSize)
+      report("insert writes past end of register", MI);
+
+    break;
+  }
   default:
     break;
   }

test/MachineVerifier/test_g_insert.mir

diff --git a/test/MachineVerifier/test_g_insert.mir b/test/MachineVerifier/test_g_insert.mir
new file mode 100644
index 0000000..0785370
--- /dev/null
+++ b/test/MachineVerifier/test_g_insert.mir
@@ -0,0 +1,44 @@
+# RUN: not llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: global-isel, aarch64-registered-target
+
+---
+name:            test_insert
+legalized:       true
+tracksRegLiveness: true
+liveins:
+body:             |
+  bb.0:
+
+    ; CHECK: Bad machine code: Too few operands
+    %0:_(s32) = G_INSERT
+
+    ; CHECK: Bad machine code: Too few operands
+    ; CHECK: Bad machine code: generic instruction must use register operands
+    %1:_(s32) = G_INSERT 0
+
+    ; CHECK: Bad machine code: generic instruction must use register operands
+    ; CHECK: Bad machine code: generic instruction must use register operands
+    ; CHECK: Bad machine code: insert source must be a register
+    %2:_(s32) = G_INSERT 0, 0, 0
+
+    %3:_(s32) = G_IMPLICIT_DEF
+    %4:_(s1) = G_IMPLICIT_DEF
+
+    ; CHECK: Bad machine code: insert writes past end of register
+    %5:_(s32) = G_INSERT %3, %4, 32
+
+    ; CHECK: Bad machine code: insert offset must be a constant
+    %5:_(s32) = G_INSERT %3, %4, %3
+
+    ; CHECK: Bad machine code: insert offset must be a constant
+    %6:_(s32) = G_INSERT %3, %4, i32 4
+
+    %7:_(s64) = G_IMPLICIT_DEF
+
+    ; CHECK: Bad machine code: inserted size must be smaller than total register
+    %8:_(s32) = G_INSERT %3, %7, 0
+
+    ; CHECK: Bad machine code: inserted size must be smaller than total register
+    %9:_(s32) = G_INSERT %3, %3, 0
+
+...