| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py | |
| # RUN: llc -mtriple=armv7-none-eabi -verify-machineinstrs -run-pass arm-ldst-opt %s -o - | FileCheck %s | |
| --- | |
| name: f | |
| # Make sure the load into $r0 doesn't clobber the base register before the second load uses it. | |
| body: | | |
| bb.0: | |
| liveins: $r0, $r3 | |
| ; CHECK-LABEL: name: f | |
| ; CHECK: $r3 = LDRi12 $r0, 12, 14 /* CC::al */, $noreg | |
| ; CHECK: $r0 = LDRi12 $r0, 8, 14 /* CC::al */, $noreg | |
| $r0, $r3 = LDRD $r0, $noreg, 8, 14, $noreg | |
| ... |